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參數(shù)資料
| 型號(hào)： | ICS9342YF-PPP-T-LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 146.62 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 175K |
| 代理商： | ICS9342YF-PPP-T-LF |
Integrated
Circuit
Systems, Inc.
ICS9342
Third party brands and names are the property of their respective owners.
9342 Rev E 9/06/00
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
Power PC System Clock
Output Features:
12- CPUs @ 3.3V, up to 146MHz
1- PCIREF @ 3.3V, up to 73MHz
1 - OUT 3.3V, 64MHz
1 - OUT/2 3.3V, OUT/2MHz
2 - REF @ 3.3V, 14.318MHz
Features:
Up to 146MHz frequency support
Support power management: CPU, PCI stop and power
down mode.
Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
Uses external 14.318MHz crystal
FS pins for frequency select
Support for industrial temperature range (-40C° to 85C°)
Key Specifications:
CPU Output Skew: <200ps
CPU - PCI Output Skew: <500ps
CPU Output Jitter: <150ps
PCI Output Jitter: <500ps
133MHz Clock Generator and Integrated Buffer for PowerPC
VDDREF
REF1
REF0
GNDREF
X1
X2
*PD#
*CPU-STOP#
VDD
GND
*PCI_STOP#
*SS_EN#
VDDPCI
PCIREF
GNDPCI
*FS0
*FS1
*FS2
VDDFP
GNDFP
*TEST#/OUT
*BOOST#/OUT_DIV2
*PDFP#
VDDA
OUTSEL1*
VDDCPU
GNDCPU
CPU0
CPU1
CPU2
VDDCPU
GNDCPU
CPU3
CPU4
CPU5
VDDCPU
GNDCPU
CPU6
CPU7
CPU8
VDDCPU
GNDCPU
CPU9
CPU10
CPU11
VDDCPU
GNDCPU
OUTSEL0*
ICS9342
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
* Internal pull-up resistor of 120K to VDD
on indicated inputs.
Functionality
Block Diagram
SS_EN#
OUTSEL (1:0)
PLL2
PLL1
Spread
Spectrum
OUT
OUT/DIV2
CPUCLK (11:0)
12
2
PCIREF
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
Stop
FS (2:0)
PD#
PDFP#
TEST#
BOOST#
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
T
S
E
T2
S
F1
S
F0
S
F
U
P
C
z
H
M
I
C
P
z
H
M
F
E
R
z
H
M
11
1
3
.
3
13
3
.
3
38
1
3
.
4
1
11
1
0
.
0
13
3
.
3
38
1
3
.
4
1
11
0
1
3
.
3
83
3
.
3
38
1
3
.
4
1
11
0
6
.
6
63
3
.
3
38
1
3
.
4
1
10
1
3
.
3
16
6
.
6
68
1
3
.
4
1
10
1
0
.
0
16
6
.
6
68
1
3
.
4
1
10
0
1
3
.
3
86
6
.
6
68
1
3
.
4
1
10
0
6
.
6
66
6
.
6
68
1
3
.
4
1
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9342YF-T | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
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| ICS93701YGT | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:DDR Phase Lock Loop Clock Driver |
| ICS93705 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93705YF-T | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
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