參數(shù)資料
型號: ICS9250YF-18LF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: ROHS COMPLIANT, SSOP-56
文件頁數(shù): 1/16頁
文件大?。?/td> 311K
代理商: ICS9250YF-18LF
ICS9250-18
Integrated
Circuit
Systems, Inc.
0387C—09/08/05
Frequency Generator & Integrated Buffers for Celeron & PII/III
Functionality
Pin Configuration
Recommended Application:
BX, Appollo Pro 133 type of chip set.
Output Features:
3 - CPUs @2.5V, up to 166MHz.
17 - SDRAM @ 3.3V, up to 166MHz.
7 - PCI @3.3V
2 - IOAPIC @ 2.5V
1 - 48MHz, @3.3V fixed.
1 - 24MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
Features:
Up to 166MHz frequency support
Support power management: CPU, PCI, stop and
Power down Mode form I
2C programming.
Spread spectrum for EMI control (± 0.25% center
spread)
Uses external 14.318MHz crystal
Key Specifications:
CPU – CPU: <175ps
CPU – PCI: 1 - 4ns
PCI – PCI: <500ps
SDRAM - SDRAM: <250ps
56-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
** Internal Pull-down resistor of 240K to GND on indicated
inputs. 1. This output is double strength.
VDDREF
*FS2/REF1
*PCI_STOP#/REF0
GND
X1
X2
VDDPCI
*MODE/PCICLK_F
*FS3/PCICLK0
GND
VDDPCI
BUFFERIN
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
SDRAM15
SDRAM14
GND
SDATA
SCLK
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
VDDLIOAPIC
IOAPIC0
IOAPIC_F
GND
CPUCLK_F
CPUCLK1
VDDLCPU
CPUCLK2
GND
CPU_STOP#
SDRAM_F
VDDSDR
SDRAM0
SDRAM1
GND
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM12
SDRAM13
VDD48
24MHz/FS0*
48MHz/FSI*
1
ICS9250-18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
{
I C
2
Block Diagram
3
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15
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3
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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