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參數(shù)資料
| 型號(hào)： | ICS9248YG-171-T |
| 英文描述： | AMD - K7TM System Clock Chip |
| 中文描述： | AMD公司- K7TM系統(tǒng)時(shí)鐘芯片 |
| 文件頁(yè)數(shù)： | 12/15頁(yè) |
| 文件大小： | 210K |
| 代理商： | ICS9248YG-171-T |
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12
ICS9248-171
Advance Information
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PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the
ICS9248-171
. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the
ICS9248-171
internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-171 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248-171.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ICS9248YG-192-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for Transmeta Systems |
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| ICS9248YG-50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| ICS9248YG-50T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| ICS9248YG-50-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
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