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參數(shù)資料
| 型號(hào)： | ICS9248YF-96-T |
| 英文描述： | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| 中文描述： | 頻率發(fā)生器 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大小： | 206K |
| 代理商： | ICS9248YF-96-T |
Integrated
Circuit
Systems, Inc.
ICS9248-96
0311D—04/23/04
Block Diagram
Recommended Application:
810/810E type chipset.
Output Features:
2- CPUs @ 2.5V, up to 166.5MHz.
9 - SDRAM @ 3.3V, up to 155MHz including
1 free running
8 - PCICLK @ 3.3V
1 - IOAPIC @ 2.5V,
2 - 3V66MHz @ 3.3V, 2X PCI MHz
2 - 48MHz, @ 3.3V fixed.
1 - 24/48MHz, @3.3V selectable by I
2
C
1 - REF @v3.3V, 14.318MHz.
Features:
Up to 166.5MHz frequency support
Support FS0-FS3 strapping status bit for I
2
C read
back.
Support power management: Through Power down
Mode from I
2
C programming.
Spread spectrum for EMI control ( ± 0.25% center).
Uses external 14.318MHz crystal
Skew Specifications:
CPU – CPU: <175ps
SDRAM - SDRAM: < 250ps
3V66 – 3V66: <175ps
PCI – PCI: <500ps
CPU-SDRAM<500ps
For group skew specifications, please refer to group
timing relationship table.
Functionality
Pin Configuration
48-Pin 300mil SSOP
* These inputs have a 120K pull up to VDD.
** 60K pull-up to VDD on indicated input
1 These are double strength.
Frequency Generator & Integrated Buffers for Celeron & P
II
/
III
Additional frequencies selectable through I
2
C
programming.
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