參數(shù)資料
型號: ICS9248yF-77
英文描述: Replaced by SN74ABT16373A : 16-Bit Transparent D-Type Latches With 3-State Outputs 48-SSOP -40 to 85
中文描述: 頻率的奔騰II系統(tǒng)時序發(fā)生器
文件頁數(shù): 8/11頁
文件大?。?/td> 100K
代理商: ICS9248YF-77
8
ICS9248-185
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the
ICS9248-185
. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the
ICS9248-185
internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. CLK_STOP# is shown in a high (true) state.
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CLK_STOP#
PCICLK [6:0]
PCI_STOP#
相關(guān)PDF資料
PDF描述
ICS9248yF-78 16-Bit Transparent D-Type Latches With 3-State Outputs 48-TSSOP -40 to 85
ICS9248yF-81 Frequency Generator & Integrated Buffers
ICS9248yF-87 16-Bit Transparent D-Type Latches With 3-State Outputs 48-TSSOP -40 to 85
ICS9248yF-97-T 16-Bit Transparent D-Type Latches With 3-State Outputs 48-SSOP -40 to 85
ICS9248yF-98-T 16-Bit Transparent D-Type Latches With 3-State Outputs 48-SSOP -40 to 85
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