參數(shù)資料
型號: ICS9248BF-138
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 2/12頁
文件大?。?/td> 0K
描述: IC FREQ GENERATOR/BUFFER 48-SSOP
標(biāo)準(zhǔn)包裝: 30
類型: 時(shí)鐘/頻率發(fā)生器,扇出緩沖器(分配)
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: 晶體
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:26
差分 - 輸入:輸出: 無/無
頻率 - 最大: 200MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 48-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 48-SSOP
包裝: 管件
其它名稱: 9248BF-138
10
ICS9248-138
0342C—08/26/03
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) on the ICS9248-
138 serve as dual signal functions to the device. During
initial power-up, they act as input pins. The logic level
(voltage) that is present on these pins at this time is read
and stored into a 5-bit internal data latch. At the end of
Power-On reset, (see AC characteristics for timing values),
the device changes the mode of operations for these pins
to an output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
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