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參數(shù)資料
| 型號(hào)： | ICS9248-78 |
| 英文描述： | Frequency Timing Generator for Pentium II Systems |
| 中文描述： | 頻率的奔騰II系統(tǒng)時(shí)序發(fā)生器 |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大?。?/td> | 100K |
| 代理商： | ICS9248-78 |
8
ICS9248-185
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the
ICS9248-185
. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the
ICS9248-185
internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only three rising PCICLK clocks, off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. CLK_STOP# is shown in a high (true) state.
CPUCLK
(Internal)
PCICLK_F
(Internal)
PCICLK_F
(Free-running)
CLK_STOP#
PCICLK [6:0]
PCI_STOP#
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| ICS9248-81 | Frequency Generator & Integrated Buffers |
| ICS9248-87 | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248-92 | Mobile Pentium IITM System Clock Chip |
| ICS9248-96 | 20-Bit Bus-Interface D-Type Latches With 3-State Outputs 56-SSOP -40 to 85 |
| ICS9248-97 | Frequency Timing Generator for PENTIUM II Systems |
相關(guān)代理商/技術(shù)參數(shù) |
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| ICS9248-80 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:General Purpose 133MHz System Clock |
| ICS9248-81 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Frequency Generator & Integrated Buffers |
| ICS9248-87 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248-90 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9248-92 | 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Mobile Pentium IITM System Clock Chip |
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