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參數(shù)資料
| 型號(hào)： | ICS9248-163 |
| 英文描述： | AMD - K7 System Clock Chip |
| 中文描述： | AMD公司- k7的系統(tǒng)時(shí)鐘芯片 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 100K |
| 代理商： | ICS9248-163 |
7
ICS9248-185
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CLK_STOP# is synchronized by the
ICS9248-185
. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-185.
3. All other clocks continue to run undisturbed.
PCICLK
SDRAM
CPUCLK
CPUCLK _F
SDRAM_F
PCI_STOP# (High)
CLK_STOP#
INTERNAL
CPUCLK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS9248F-151-T | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| ICS9248F-163-T | AMD - K7 System Clock Chip |
| ICS9248yF-72 | Frequency Timing Generator for PENTIUM II Systems |
| ICS9248-72 | 20-Bit Buffers/Drivers With 3-State Outputs 56-SSOP -40 to 85 |
| ICS9248-73 | Frequency Timing Generator for Pentium II Systems |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9248-168 | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K7⑩ Clock Generator for Mobile System |
| ICS9248-171 | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K7TM System Clock Chip |
| ICS9248-185 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM & K6 |
| ICS9248-189 | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K7⑩ Clock Generator for Mobile System |
| ICS9248-192 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for Transmeta Systems |
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