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參數(shù)資料
| 型號： | ICS9222YG-01-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9222 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 2 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 93K |
| 代理商： | ICS9222YG-01-T |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9222- 01
0274C—11/14/05
Block Diagram
Dual Memory Clock Generator
Pin Configuration
The ICS9222-01 is a High-speed clock generator providing
two channels up to 450 MHz differential clock source for
direct Rambus_memory system. It includes two independent
DDLL’s (Distributed Delay locked loop) and phase detection
mechanisms to synchronize eachdirect Rambus_ channel
clock to an external system clock. ICS9222-01 provides a
solution for a broad range of Direct Rambus memory
applications. The device works in conjunction with the
ICS964S101, as well as 9250-22 and others (depending on
chipset).
The ICS9222-01 power management support system turns
“off” the Rambus channel clock to minimize power
consumption for mobile and other power sensitive
applications. In “clock off” mode the device remains “on”
while the output is disabled, allowing fast transitions between
clock-off and clock–on states. In “power down” mode it
completely powers down for minimum power dissipation.
28-Pin TSSOP
Compatible with all Direct Rambus based ICs
Up to 450 MHz differential clock source for direct
Rambus memory system
Cycle to cycle jitter is less than 100 ps
3.3 ± 5% supply
Synchronization flexibility: Supports systems that need
clock domains of Rambus channel to synchronize with
system or processor clock, or systems that do not
require synchronization of the Rambus clock to another
system clock.
Excellent power management support
REFCLK input is from the main clock generator such as
a 9250-22.
VDDREF
REFCLK
VDDC
SYNCLK0
PCLK0
GND
VDDP
GND
SYNCLK1
PCLK1
VDDC
VDDIPD
CLK_STOP#
PD#
FS0
FS1
FS2
GND
CLKB0
CLK0
VDDCLK
CLK1
CLKB1
GND
MULT_0
MULT_1
MULT_2
ICS9222-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLK_STOP#
Phase
Aligner
Phase
Aligner
PCLK0
PCLK1
SYNCLK1
SYNCLK0
PD#
FS (2:0)
Test MUX
Bypass MUX
Bypclk
GND
CLK1
CLK0
CLKB1
CLKB0
Phase
Detector
Phase
Detector
PAclk
PLL
MULT (2:0)
REFCLK
PLLclk
2
B
A
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