- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360778 > ICS9148-47 Replaced by TIBPAL20R8-7M : High-Performance Impact-X<TM> PAL(R) Circuits 24-CDIP -55 to 125 PDF資料下載
參數(shù)資料
| 型號： | ICS9148-47 |
| 英文描述： | Replaced by TIBPAL20R8-7M : High-Performance Impact-X<TM> PAL(R) Circuits 24-CDIP -55 to 125 |
| 中文描述： | 奔騰/ ProTM系統(tǒng)時(shí)鐘芯片 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 691K |
| 代理商： | ICS9148-47 |
10
ICS9148-02
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internal by the
ICS9148-02
prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD#
is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the Crystal oscillator. The power
on latency is guaranteed to be less than 3mS. The power down latency is less than three CPUCLK cycles. PCI_STOP# and
CPU_STOP# are dont care signals during the power down operations.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9148.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9148 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9148.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS9148-53 | Frequency Generator & Integrated Buffers for Mother Boards |
| ICS9148-58 | Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9148-82 | Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9148-93 | High-Performance Impact<TM> PAL<R> Circuits 28-PLCC 0 to 75 |
| ICS9148yF-82 | High-Performance Impact<TM> PAL<R> Circuits 24-PDIP 0 to 75 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9148-53 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for Mother Boards |
| ICS9148-58 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9148-60 | 制造商:ICS 制造商全稱:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148-75 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for Mother Boards |
| ICS9148-82 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。