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參數(shù)資料
| 型號(hào)： | ICS9148-26 |
| 英文描述： | High-Performance Impact-X<TM> PAL(R) Circuits 24-PDIP 0 to 75 |
| 中文描述： | 頻率發(fā)生器 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 691K |
| 代理商： | ICS9148-26 |
5
ICS9148-02
CPU 3.3_2.5#
This Input pin controls the CPU and IOAPIC output buffer
strength for skew matching CPU and SDRAM outputs to
compensate for the external VDDL supply condition. It is
important to use this function when selecting power supply
requirements for VDDL1,2. A logic 0 (ground) will indicate
2.5V operation and a logic 1 will indicate 3.3V operation.
This pin has an internal pullup resistor to VDD.
PWR_DWN#
This is an asynchronous active Low Input pin used to Power
Down the device into a Low Power state by not removing the
power supply. The internal Clocks are disabled and the VCO
and Crystal are stopped. Powered Down will also place all
the Outputs in a low state at the end of their current cycle.
The latency of Power Down will not be greater than 3ms. The
I
2
C inputs will be Tri-Stated and the device will retain all
programming information. This input pin only valid when
MODE=0 (Power Management Mode)
CPU_STOP#
This is a synchronous active Low Input pin used to stop the
CPUCLK clocks in an active low state. All other Clocks
including SDRAM clocks will continue to run while this
function is enabled. The CPUCLKs will have a turn ON
latency of at least 3 CPU clocks. This input pin only valid
when MODE=0 (Power Management Mode)
PCI_STOP#
This is a synchronous active Low Input pin used to stop the
PCICLK clocks in an active low state. It will not effect
PCICLK_F nor any other outputs. This input pin only valid
when MODE=0 (Power Management Mode)
I
2
C
The SDATA and SCLOCK Inputs are use to program the
device. The clock generator is a slave-receiver device in the
I
2
C protocol. It will allow read-back of the registers. See
configuration map for register functions. The I
2
C
specification in Philips I
2
C Peripherals Data Handbook
(1996) should be followed.
Technical Pin Function Descriptions
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS9148-32 | Pentium/ProTM System Clock Chip |
| ICS9148-36 | High-Performance Impact-X<TM> PAL<R> Circuits 24-PDIP 0 to 75 |
| ICS9148-37 | Frequency Generator & Integrated Buffers for PENTIUM/Pro |
| ICS9148-46 | Replaced by TIBPAL20R8-7M : High-Performance Impact-X<TM> PAL(R) Circuits 24-CFP -55 to 125 |
| ICS9148-47 | Replaced by TIBPAL20R8-7M : High-Performance Impact-X<TM> PAL(R) Circuits 24-CDIP -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9148-32 | 制造商:ICS 制造商全稱:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148-36 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM |
| ICS9148-37 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/Pro |
| ICS9148-46 | 制造商:ICS 制造商全稱:ICS 功能描述:Pentium/ProTM System Clock Chip |
| ICS9148-47 | 制造商:ICS 制造商全稱:ICS 功能描述:Pentium/ProTM System Clock Chip |
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