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參數資料
| 型號： | ICS91309AGLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 1/10頁 |
| 文件大小： | 0K |
| 描述： | IC BUFFER ZD LOW JITTER 16-TSSOP |
| 標準包裝： | 2,500 |
| 類型： | 零延遲緩沖器 |
| PLL： | 帶旁路 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:9 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 133MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 91309AGLFT |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS91309
0093H—12/09/08
Block Diagram
High Performance Communication Buffer
Pin Configuration
Zero input - output delay
Frequency range 10 - 133 MHz (3.3V)
5V tolerant input REF
High loop filter bandwidth ideal for Spread Spectrum
applications.
Less than 125 ps cycle to cycle Jitter
Skew controlled outputs
Available in 16 pin, 150 mil SSOP, SOIC & 4.40mm
TSSOP packages
Skew: Group-to-Group: <215 ps
Skew within Group: <100 ps
Commercial temperature range: 0°C to +70°C
The ICS91309 is a high performance, low skew, low jitter
zero delay buffer.
It uses a phase lock loop (PLL)
technology to align, in both phase and frequency, the REF
input with the CLKOUT signal. It is designed to distribute
high speed clocks in communication systems operating
at speeds from 10 to 133 MHz.
The ICS91309 provides synchronization between the
input and output. The synchronization is established via
CLKOUT feed back to the input of the PLL. Since the skew
between the input and output is less than +/- 350 pS, the
part acts as a zero delay buffer.
ICS91309 has two banks of four outputs controlled by two
address lines. Depending on the selected address line,
bank B or both banks can be put in a tri-state mode. In this
mode, the PLL is still running and only the output buffers
are put in a high impedance mode. The test mode shuts
off the PLL and connects the input directly to the output
buffers (see table below for functionality).
ICS91309 comes in a 16-pin 150 mil SOIC, SSOP or
4.40mm TSSOP package. In the absence of REF input,
the device will enter a powerdown mode. In this mode, the
PLL is turned off and the output buffers are pulled low.
Power down mode provides the lowest power consumption
for a standby condition.
16 pin SSOP, SOIC & TSSOP
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
FS2
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
FS1
ICS91309
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Functionality
FS2 FS1 CLKA(1:4) CLKB(1:4)
CLKOUT
Ouput
Source
PLL
Shutdown
0
Tristate
Driven
PLL
N
0
1
Driven
Tristate
Driven
PLL
N
10
PLL
Bypass
Mode
PLL Bypass
Mode
PLL
Bypass
Mode
REF
Y
1
Driven
PLL
N
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