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參數(shù)資料
| 型號： | ICS91305AMLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK DRIVER LO JITTER 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 零延遲緩沖器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:5 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 133MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 91305AMLFT |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS91305
0092H—12/02/08
Block Diagram
High Performance Communication Buffer
Pin Configuration
Zero input - output delay
Frequency range 10 - 133 MHz (3.3V)
5V tolerant input REF
High loop filter bandwidth ideal for Spread
Spectrum applications.
Less than 200 ps Jitter between outputs
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 8 pin 150 mil SOIC & 173 mil
TSSOP packages
3.3V ±10% operation
The ICS91305 is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology
to align, in both phase and frequency, the REF input with
the CLKOUT signal. It is designed to distribute high speed
clocks in communication systems operating at speeds
from 10 to 133 MHz.
ICS91305 is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to
the input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
The ICS91305 comes in an eight pin 150 mil SOIC
package. It has five output clocks. In the absence of REF
input, will be in the power down mode. In this mode, the
PLL is turned off and the output buffers are pulled low.
Power down mode provides the lowest power consumption
for a standby condition.
8 pin SOIC & TSSOP
REF
CLK2
CLK1
GND
CLKOUT
CLK4
VDD
CLK3
ICS91305
1
2
3
4
8
7
6
5
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| ICS91305AMIT | IC CLOCK DRIVER LO JITTER 8-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS91305AMT | 功能描述:IC CLOCK DRIVER LO JITTER 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| ICS91305I | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:High Performance Communication Buffer |
| ICS91305YGILF-T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:High Performance Communication Buffer |
| ICS91305YGLFT | 制造商:ICS 制造商全稱:ICS 功能描述:High Performance Communication Buffer |
| ICS91305YMILF-T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:High Performance Communication Buffer |
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