參數(shù)資料
型號(hào)： ICS9112YM-26LFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 9112 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封裝： 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, TSSOP-8
文件頁(yè)數(shù)： 1/5頁(yè)
文件大?。?/td> 85K
代理商： ICS9112YM-26LFT
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9112-26
Block Diagram
Low Skew Output Buffer
9112-26 Rev D - 05/14/07
Pin Configuration
Frequency range 0 - 133 MHz (3.3V)
Less than 200 ps Jitter between outputs
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 8 pin 150 mil SOIC &
173 mil TSSOP packages.
3.3V ±10% operation
The ICS9112-26 is a high performance, low skew, low jitter
clock driver. It is designed to distribute high speed clocks in
PC systems operating at speeds from 0 to 133 MHz.
The ICS9112-26 comes in an eight pin 150 mil SOIC package.
It has four output clocks.
8 pin SOIC & TSSOP
CLK0
VDD
GND
CLK1
CLK_IN
CLK3
VDD
CLK2
ICS9112-26
1
2
3
4
8
7
6
5
CLK_IN
CLK0
CLK1
CLK2
CLK3
Pin Descriptions
Notes:
1.
Weak pull-down on all outputs
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ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
相關(guān)PDF資料
PDF描述
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