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參數(shù)資料
| 型號： | ICS9112M-06 |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 91 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 209K |
| 代理商： | ICS9112M-06 |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9112-06/07
Block Diagram
Low Skew Output Buffer
9112-06/07 Rev H 1/22/99
Pin Configuration
16 pin SOIC
Zero input - output delay
Frequency range 25 - 75 MHz (3.3V), 30-90MHz (5.0V)
Less than 200 ps Jitter between outputs
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 8 or 16 pin versions, 150 mil SOIC packages
3.3V ±10%, 5.0V±10% operation
The ICS9112 is a high performance, low skew, low jitter clock
driver. It uses a phase lock loop (PLL) technology to align, in
both phase and frequency, the REF input with the CLKOUT
signal. It is designed to distribute high speed clocks in PC
systems operating at speeds from 25 to
75 MHz (30 to 90mHz for 5V operation).
ICS9112 is a zero delay buffer that provides synchronization
between the input and output. The synchronization is
established via CLKOUT feed back to the input of the PLL.
Since the skew between the input and output is less than +/-
350 pS, the part acts as a zero delay buffer.
The ICS9112 comes in with two different options; dash 06
and dash 07. The dash 07 is available in a 16 pin 150 mil SOIC
package. It has two banks of four outputs controlled by two
address lines. Depending on the selected address line, bank B
or both banks can be put in a tri-state mode. In this mode, the
PLL is still running and only the output buffers are put in a
high impedance mode. The test mode shuts off the PLL and
connects the input directly to the output buffers (see table
below for functionality).
The dash 06 is an eight pin 150 mil SOIC package. It has five
output clocks. In the absence of REF input, both ICS9112-06
and -07 will be in the power down mode. In this mode, the
PLL is turned off and the output buffers are pulled low. Power
down mode provides the lowest power consumption for a
standby condition.
8 pin SOIC
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Functionality (-07)
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all device
data to verify that any information being relied upon by the customer is current and accurate.
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PDF描述 |
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| ICS9120M-45 | 50 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| ICS91305YGI-T | 91305 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9112M-07 | 制造商:ICS 制造商全稱:ICS 功能描述:Low Skew Output Buffer |
| ICS9112M-22 | 功能描述:IC CLK BUFFER DVR 133MHZ 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:- 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ICS9112M-31 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator for Fibre Channel Systems |
| ICS9112M-32 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator for Fibre Channel Systems |
| ICS9112M-33 | 功能描述:IC CLOCK DRIVER LO JITTER 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
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