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參數(shù)資料
| 型號： | ICS879893BYIT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 879893 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 233K |
| 代理商： | ICS879893BYIT |
Integrated
Circuit
Systems, Inc.
879893BYI
www.icst.com/products/hiperclocks.html
REV. A JULY 12, 2005
1
ICS879893BI
LOW SKEW, 1-TO-12 (IDCS)
LVCMOS/LVTTL CLOCK GENERATOR
PRELIMINARY
GENERAL DESCRIPTION
The ICS879893BI is a PLL clock driver design-
ed specifically for redundant clock tree
designs. The device receives two LVCMOS/
LVTTL clock signals from which it generates 12
new LVCMOS/LVTTL clock outputs. External
PLL feedback is used to also provide zero de-
lay buffer performance.
The ICS879893BI Intelligent Dynamic Clock Switch (IDCS)
circuit continuously monitors both input CLK signals. Upon
detection of a failure (CLK stuck HIGH or LOW for at least
1 period), the nALARM for that CLK will be latched (LOW).
If that CLK is the primary clock, the IDCS will switch to
the good secondary clock and phase/frequency alignment
will occur with minimal output phase disturbance.
HiPerClockS
ICS
QA0:QA5
QB0:QB5
QFB
nALARM0
nALARM1
CLK_IND
PIN ASSIGNMENT
nOE/MR
CLK0
CLK1
FB
REF_SEL
nMAN/A
nALARM_RST
nPLL_EN
FSEL[0:2]
FSEL3
D Q
÷2
0
1
0
1
REF
FB
PLL
VCO Range
240MHz-500MHz
IDCS
0
÷2
0
1
÷2
0
1
0
÷2
0
1
÷4
1
0
÷2
1
0
1
÷16
1
0
÷8
1
÷4
SIMPLIFIED BLOCK DIAGRAM
FEATURES
12 LVCMOS/LVTTL outputs (2 banks of 6 outputs);
1 QFB feedback clock output
Selectable CLK0 or CLK1 LVCMOS/LVTTL clock inputs
CLK0, CLK1 supports the following input types:
LVCMOS, LVTTL
Automatically detects clock failure
IDCS on-chip intelligent dynamic clock switch
Maximum output frequency: 200MHz
Output skew: 25ps (typical), within bank
Cycle-to-cycle (FSEL3=0, V
DD=3.3V±5%): 20ps (typical)
Smooth output phase transition during clock failover switch
Full 3.3V or 2.5V operating supply
-40°C to 85°C ambient operating temperature
GND
QFB
FB
nMAN/A
V
DD
CLK0
CLK1
V
DDA
nALARM0
nALARM1
CLK_IND
GND
36 35 34 33 32 31 30 29 28 27 26 25
1 2 3 4 5 6 7 8 9 10 11 12
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
GND
QA0
QA1
VDD
GND
QA2
QA3
VDD
GND
QA4
QA5
VDD
GND
QB0
QB1
VDD
GND
QB2
QB3
VDD
GND
QB4
QB5
VDD
V
DD
nALARM_RST
REF_SEL
nPLL_EN
GND
FSEL0
FSEL1
GND
FSEL2
FSEL3
nOE/MR
V
DD
ICS879893BI
48-Pin LQFP
7mm x 7mm x 1.4mm
body package
Y Package
Top View
FSEL0 FSEL1 FSEL2
0
÷16
0
1
÷8
0
1
0
÷6
0
1
÷8
1
0
÷4
1
0
1
÷16
1
0
÷8
1
÷4
FSEL0 FSEL1 FSEL2
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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