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參數(shù)資料
| 型號： | ICS87608AYIT |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LOW VOLTAGE/LOW SKEW, 1:8 PCI/PCI-X ZERO DELAY CLOCK GENERATOR |
| 中文描述： | 低電壓/低偏移，1:8的PCI / PCI - X的零延遲時鐘發(fā)生器 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 152K |
| 代理商： | ICS87608AYIT |
87608AYI
www.icst.com/products/hiperclocks.html
REV. B MARCH 11, 2005
1
Integrated
Circuit
Systems, Inc.
ICS87608I
L
OW
V
OLTAGE
/L
OW
S
KEW
, 1:8 PCI/PCI-X
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS87608I has a selectable REF_CLK or
crystal input. The REF_CLK input accepts
LVCMOS or LVTTL input levels. The ICS87608I
has a fully integrated PLL along with frequency
configurable clock and feedback outputs for
multiplying and regenerating clocks with “zero delay”.
The ICS87608I is a 1:8 PCI/PCI-X Clock Generator and a
member of the HiPerClockS
TM
family of high performance clock
solutions from ICS. The ICS87608I has a selectable REF_CLK
or crystal input. The REF_CLK input accepts LVCMOS or
LVTTL input levels. The ICS87608I has a fully integrated PLL
along with frequency configurable clock and feedback outputs
for multiplying and regenerating clocks with “zero delay”. The
PLL’s VCO has an operating range of 250MHz-500MHz,
allowing this device to be used in a variety of general purpose
clocking applications. For PCI/PCI-X applications in particular,
the VCO frequency should be set to 400MHz. This can be
accomplished by supplying 33.33MHz, 25MHz, 20MHz, or
16.66MHz on the reference clock or crystal input and by
selecting ÷12, ÷16, ÷20, or ÷24, respectively as the feedback
divide value. The dividers on each of the two output banks
can then be independently configured to generate 33.33MHz
(÷12), 66.66MHz (÷6), 100MHz (÷4), or 133.33MHz (÷3).
The ICS87608I is characterized to operate with its core supply
at 3.3V and each bank supply at 3.3V or 2.5V. The ICS87608I
is packaged in a small 7x7mm body LQFP, making it ideal for
use in space-constrained applications.
F
EATURES
Fully integrated PLL
8 LVCMOS/LVTTL outputs, 15
Ω
typical output impedance
Selectable crystal oscillator interface or
LVCMOS/LVTTL REF_IN clock input
Maximum output frequency: 166.67MHz
Maximum crystal input frequency: 38MHz
Maximum REF_IN input frequency: 41.67MHz
Individual banks with selectable output dividers for
generating 33.333MHz, 66.66MHz, 100MHz and
133.333MHz
Separate feedback control for generating PCI / PCI-X
frequencies from a 16.66MHz or 20MHz crystal, or 25MHz
or 33.33MHz reference frequency
VCO range: 200MHz to 500MHz
Cycle-to-cycle jitter: 120ps (maximum), @ 3.3V
Period jitter, RMS: 20ps (maximum)
Output skew: 250ps (maximum)
Bank skew: 60ps (maximum)
Static phase offset: 160ps ± 160ps
Voltage Supply Modes:
V
DD
(core/inputs), V
(analog supply for PLL),
V
DDOA
(output bank A),
V
DDOB
(output bank B, REF_OUT, FB_OUT)
V
DD
/V
DDA
/V
DDOA
/V
DDOB
3.3/3.3/3.3/3.3
3.3/3.3/2.5/3.3
3.3/3.3/3.3/2.5
3.3/3.3/2.5/2.5
Lead-Free package fully RoHS compliant
-40°C to 85°C ambient operating temperature
HiPerClockS
ICS
P
IN
A
SSIGNMENT
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
QB0
QB1
GND
QB2
QB3
V
DDOB
REF_OUT
FB_OUT
QA0
QA1
GND
QA2
QA3
V
DDOA
MR
DIV_SELA0
G
F
V
D
F
F
D
D
D
V
D
P
V
D
X
X
X
R
V
D
ICS87608I
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y package
Top View
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