參數(shù)資料
型號: ICS8745BYI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 8745 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
文件頁數(shù): 3/20頁
文件大?。?/td> 1383K
代理商: ICS8745BYI
ICS8745BI
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
IDT / ICS LVDS ZERO DELAY CLOCK GENERATOR
11
ICS8745BYIREV. C APRIL 16, 2007
Differential Clock Input Interface
The CLK /CLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both signals must meet the VPP and
VCMR input requirements. Figures 3A to 3D show interface
examples for the HiPerClockS CLK/CLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
Figure 3A. HiPerClockS CLK/CLK Input Driven by an
IDT HiPerClockS LVHSTLDriver
Figure 3C. HiPerClockS CLK/CLK Input
Driven by a 3.3V LVPECL Driver
Figure 3B. HiPerClockS CLK/CLK Input
Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/CLK Input Driven by
a 3.3V LVDS Driver
R1
50
R2
50
1.8V
Zo = 50
Zo = 50
CLK
nCLK
3.3V
LVHSTL
IDT
HiPerClockS
LVHSTL Driver
HiPerClockS
Input
R3
125
R4
125
R1
84
R2
84
3.3V
Zo = 50
Zo = 50
CLK
nCLK
3.3V
LVPECL
HiPerClockS
Input
CLK
nCLK
HiPerClockS
Input
LVPECL
3.3V
Zo = 50
Zo = 50
3.3V
R1
50
R2
50
R2
50
3.3V
R1
100
LVDS
CLK
nCLK
3.3V
Receiver
Zo = 50
Zo = 50
相關(guān)PDF資料
PDF描述
ICS874S02AMILF 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
ICS874S02AMI 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
ICS874S02AMIT 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
ICS874S02BMILF 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
ICS874S02BMI 874S SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
相關(guān)代理商/技術(shù)參數(shù)
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ICS874S02BMI 制造商:Integrated Device Technology Inc 功能描述:IC CLK GENERATOR ZDB 20SOIC