參數(shù)資料
型號: ICS8745BM-21LF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 17/19頁
文件大小: 0K
描述: IC CLK GEN ZD DIFF-LVDS 20-SOIC
標(biāo)準(zhǔn)包裝: 37
系列: HiPerClockS™
類型: 時鐘發(fā)生器
PLL: 帶旁路
輸入: HCSL,LVDS,LVHSTL,LVPECL,SSTL
輸出: LVDS
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 700MHz
除法器/乘法器: 是/是
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC
包裝: 管件
其它名稱: 800-1218
800-1218-5
800-1218-ND
8745BM-21LF
ICS8745BM-21 REVISION D JANUARY 25, 2010
7
2010 Integrated Device Technology, Inc.
ICS8745B-21 Data Sheet
1:1 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when
the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
NOTE 7: Measured from the 20% to 80% points. Guaranteed by characterization. Not production tested.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
700
MHz
tPD
Propagation Delay; NOTE 1
PLL_SEL = 0V, f
≤ 700MHz
3.1
3.4
4.0
ns
tsk()
Static Phase Offset; NOTE 2, 5
PLL_SEL = 3.3V
-100
25
150
ps
tsk(o)
Output Skew; NOTE 3, 5
35
ps
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 5, 6
30
ps
tjit(
θ)
Phase Jitter; NOTE 4, 5, 6
±52
ps
tL
PLL Lock Time
1ms
tR / tF
Output Rise/Fall Time; NOTE 7
20% to 80%
200
700
ps
odc
Output Duty Cycle
46
50
54
%
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