參數(shù)資料
型號(hào): ICS874004AG
英文描述: PCI EXPRESS JITTER ATTENUATOR
中文描述: PCI Express抖動(dòng)衰減
文件頁數(shù): 1/10頁
文件大?。?/td> 182K
代理商: ICS874004AG
Integrated
Circuit
Systems, Inc.
874004AG
www.icst.com/products/hiperclocks.html
REV. A JANUARY 21, 2005
1
ICS874004
PCI E
XPRESS
J
ITTER
A
TTENUATOR
PRELIMINARY
G
ENERAL
D
ESCRIPTION
The ICS874004 is a high performance Differential-
to HCSL Jitter Attenuator designed for use in PCI
Express systems. In some PCI Express
systems, such as those found in desktop PCs, the
PCI Express clocks are generated from a low
bandwidth, highphase noise PLL frequency synthesizer. In these
systems, a jitter attenuator may be required to attenuate high
frequency random and deterministic jitter components from the
PLL synthesizer and from the system board. The ICS874004
has 3 PLL bandwidth modes: 200KHz, 400KHz, and 800KHz.
200KHz mode will provide maximum jitter attenuation, but with
higher PLL tracking skew and spread spectrum modulation from
the motherboard synthesizer may be attenuated. 400KHz
provides an intermediate bandwidth that can easily track
triangular spread profiles, while providing good jitter attenuation.
800KHz bandwidth provides the best tracking skew and will pass
most spread profiles, but the jitter attenuation will not be as good
as the lower bandwidth modes. Because some 2.5 Gb serdes
have x20 multipliers while others have than x25 multipliers, the
874004 can be set for 1:1 mode or 5/4 multiplication mode (i.e.
100MHz input/125MHz output) using the F_SEL pin.
The ICS874004 uses ICS 3
rd
Generation FemtoClock
TM
PLL technology to achieve the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package, making
it ideal for use in space constrained applications such as PCI
Express add-in cards.
Features
(4) Differential LVDS output pairs
(1) Differential clock input
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Output frequency range: 98MHz - 160MHz
Input frequency range: 98MHz - 128MHz
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 50ps (maximum) design target
3.3V operating supply
3 bandwidth modes allow the system designer to make jitter
attenuation/tracking skew design trade-offs
0°C to 70°C ambient operating temperature
HiPerClockS
ICS
QA0
nQA0
B
LOCK
D
IAGRAM
BW_SEL
0 = PLL Bandwidth: ~200KHz
Float = PLL Bandwidth: ~400KHz (Default)
1 = PLL Bandwidth: ~800KHz
PLL B
ANDWIDTH
0 ÷5
(default)
1 ÷4
÷5
VCO
490-640MHz
Phase
Detector
PD
OEA
F_SEL
BW_SEL
0 = ~200KHz
Float = ~400KHz
1 = ~800KHz
CLK
nCLK
FB_IN
nFB_IN
MR
OEB
PU
QA1
nQA1
QB0
nQB0
QB1
nQB1
FB_OUT
nFB_OUT
PD
PD
PD
PU
PU
PU
Float
P
IN
A
SSIGNMENT
ICS874004
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
G Package
Top View
nQA0
nQB0
QB0
V
DDO
FB_OUT
nFB_OUT
MR
BW_SEL
V
DDA
F_SEL
V
DD
OEA
1
2
3
4
5
6
7
8
9
10
11
12
QA0
V
DDO
QA1
nQA1
QB1
nQB1
nFB_IN
FB_IN
OEB
GND
nCLK
CLK
24
23
22
21
20
19
18
17
16
15
14
13
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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ICS874005AG-04LF 功能描述:IC PCI EXPRSS/JITT ATTEN 24TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:HiPerClockS™, FemtoClock™, PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器,多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器,RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6
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ICS874005AGLF 功能描述:IC JITTER ATTENUATOR 24-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:HiPerClockS™, FemtoClock™, PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/頻率發(fā)生器,多路復(fù)用器 PLL:是 主要目的:存儲(chǔ)器,RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP(0.173",4.40mm 寬) 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6
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