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參數(shù)資料
| 型號(hào)： | ICS873996AY |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 873996 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, MS-026ABC-HD, TQFP-48 |
| 文件頁數(shù)： | 3/21頁 |
| 文件大?。?/td> | 352K |
| 代理商： | ICS873996AY |
IDT / ICS 3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER
11
ICS873996AY REV. A FEBRUARY 19, 2008
ICS873996
DIFFERENTIAL-TO-3.3V LVPECL ZERO DELAY/MULTIPLIER/DIVIDER
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLKx
nCLKx
VCC
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS873996
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC, VCCA and
V
CCOx
should be individually connected to the power supply plane
through vias, and 0.01F bypass capacitors should be used for
each pin.
Figure 1 illustrates this for a generic V
CC pin and also
shows that V
CCA requires
that an additional 10
Ω resistor
along with a 10F bypass capacitor be connected to the V
CCA pin.
FIGURE 1. POWER SUPPLY FILTERING
10
Ω
V
CCA
10
μF
.01
μF
3.3V
.01
μF
V
CC
POWER SUPPLY FILTERING TECHNIQUES
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