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參數資料
| 型號： | ICS8735AYI-01 |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 8735 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 |
| 文件頁數： | 2/17頁 |
| 文件大小： | 283K |
| 代理商： | ICS8735AYI-01 |
8735AYI-01
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 12, 2004
10
Integrated
Circuit
Systems, Inc.
ICS8735I-01
1:5 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY CLOCK GENERATOR
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C1, C6, C2, C4, C5, and C7,
as close as possible to the power pins. If space allows, place-
ment of the decoupling capacitor on the component side is
preferred. This can reduce unwanted inductance between the
decoupling capacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
CCA pin as possible.
CLOCK TRACES AND TERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital sys-
tems, the clock signal is less tolerant to poor signal integrity
than other signals. Any ringing on the rising or falling edge
or excessive ring back can cause system failure. The shape
of the trace and the trace delay might be restricted by the
available space on the board and the component location.
While routing the traces, the clock signal traces should be routed
first and should be locked prior to routing other signal traces.
The differential 50
output traces should have same
length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
FIGURE 5B. PCB BOARD LAYOUT FOR ICS8735I-01
GND
C7
C16
VCCA
VIA
U1
VCC
C4
50 Ohm
Traces
C1
C6
VCCO
R7
C5
C2
Pin 1
C11
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