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參數(shù)資料
| 型號(hào)： | ICS8733BY-01T |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大?。?/td> | 205K |
| 代理商： | ICS8733BY-01T |
8733BY-01
www.icst.com/products/hipercocks.html
REV. A JANUARY 17, 2002
2
Integrated
Circuit
Systems, Inc.
ICS8733-01
700MHZ FORWARD ERROR CORRECTION
DIFFERENTIAL-TO-3.3V LVPECL CLOCK GENERATOR
PRELIMINARY
FUNCTIONAL DESCRIPTION
The ICS8733-01 features a fully integrated PLL and therefore requires no external component for setting the loop bandwidth.
The ICS8733-01 will generate an output having a frequency as follows:
The M and N bits are controlled by the FEC_NSEL and FEC_MSEL control pins as shown in
Table 3A and Table 3B.
As a result, FOUT0 can be configured to have an output frequency equal to 14/15, 15/14, 14/14, or 15/15 of the reference
input frequency.
The second output clock (FOUT1) is configured to produce a frequency equal to FOUT0, FOUT/2, FOUT0/4, or FOUT0x4,
dependent upon the DIV_SEL0 and DIV_SEL1 bits as shown in
Table 3C and 3D.
The reference input frequency range is dependent upon not only the M and N bits, but also upon the FOUT1 output
configuration which is determined by the DIV_SEL0 and DIV_SEL1 bits.
Table 3C shows the possible FOUT0 and
FOUT1 output configurations as well as the reference input frequency range for each of these configurations.
The ICS8733-01 also supports in-circuit testing and on-chip functional block characterization via two test inputs and
one test output. With the ICS8733-01 in PLL bypass mode (PLL_SEL = 0), the reference input bypasses the PLL and
in-circuit testing of the N, M, and output dividers can take place.
Table 3D shows the output configurations for the
different combinations of the DIV_SEL1 and DIV_SEL0 pins.
fREF_CLK x M
N
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