8731CY-01
www.idt.com
REV. B JULY 27, 2010
10
ICS8731-01
LOW SKEW, 1-TO-11 DIFFERENTIAL-TO-3.3V LVPECL
CLOCK MULTIPLIER / ZERO DELAY BUFFER
Zo = 50
To Logic
Input
pins
U1
8731-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
MR
V
CCO
Q8
nQ
8
Q9
nQ
9
VEE
Q
10/
Q
F
B
nQ
10/
nQ
F
B
V
CCO
FB
_
IN
nF
B
_I
N
nc
VEE
VCC
FB_SEL0
FB_SEL1
nREF_CLK
REF_CLK
VEE
VCCA
DIV_SEL0
DIV_SEL1
DIV_SEL2
VC
C
O
nQ
3
Q3
nQ
2
Q2
VEE
nQ
1
Q1
nQ
0
Q0
VC
C
O
nc
VCCO
nQ7
Q7
nQ6
Q6
VEE
nQ5
Q5
nQ4
Q4
VCCO
PLL_SEL
R5
50
R10
50
(U1-26)
VCC
+
-
C4
0.1uF
C16
10uF
C5
0.1uF
C1
0.1uF
R9
50
Bypass capacitors located near the power pins
Zo = 50
C3
0.1uF
C2
0.1uF
(U1-10)
VCC=3.3V
VCCA
C11
0.1uF
(U1-48)
VCC
R2
50
R4
50
Set Logic
Input to
'1'
VCCO=3.3V
VCCO
R1
50
RD1
SPARE
VCCO
3.3V
Zo = 50
R8
50
Zo = 50
C6
0.1uF
VCC
Logic Input Pin Examples
RU1
1K
RD2
1K
(U1-38)
R13
10
R3
50
+
-
R6
50
(U1-36)
R7
50
RU2
SPARE
C11
0.1uF
R11
50
VCC
LVPECL
(U1-2)
Set Logic
Input to
'0'
Zo = 50
To Logic
Input
pins
R12
50
SCHEMATIC EXAMPLE
Figure 5 shows an application schematic example of the
ICS8731-01. This schematic provides examples of input and
output handling. The input can accept various types of differen-
tial signal. This example shows the ICS8731-01 input driven by
a 3.3V LVPECL driver. Additional examples for the input driven
by other types of drivers are shown in the application section of
FIGURE 5. APPLICATION SCHEMATIC EXAMPLE
this data sheet. The ICS8731-01 outputs are LVPECL driver. In
this example, we assume the traces are long transmission line
and the receiver is high input impedance without built-in matched
load. An example of 3.3V LVPECL termination is shown in this
schematic. Additional termination approaches are shown in the
LVPECL Termination Application Note.