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參數(shù)資料
| 型號： | ICS8725AM-21LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 8725 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | 7.50 X 12.80 MM, 2.30 MM HEIGHT, LEAD FREE, MS-013, MO-119, SOIC-20 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大小： | 130K |
| 代理商： | ICS8725AM-21LF |
8725AM-21
www.icst.com/products/hiperclocks.html
REV. A MAY 22, 2006
1
Integrated
Circuit
Systems, Inc.
ICS8725-21
DIFFERENTIAL-TO-HSTL
ZERO DELAY CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS8725-21 is a highly versatile 1:1 Differ-
ential-to-HSTL Clock Generator and a member
of the HiPerClockS family of High Performance
Clock Solutions from ICS. The CLK, nCLK pair
can accept most standard differential input lev-
els. The ICS8725-21 has a fully integrated PLL and can be
configured as zero delay buffer, multiplier or divider, and has
an output frequency range of 31.25MHz to 630MHz. The ref-
erence divider, feedback divider and output divider
are each programmable, thereby allowing for the following out-
put-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8.
The external feedback allows the device to achieve “zero
delay” between the input clock and the output clocks. The
PLL_SEL pin can be used to bypass the PLL for system test
and debug purposes. In bypass mode, the reference clock
is routed around the PLL and into the internal output dividers.
FEATURES
One differential HSTL output pair,
One differential feedback output pair
Differential CLK, nCLK input pair
CLK, nCLK pair can accept the following differential
input levels: LVDS, LVPECL, HSTL, SSTL, HCSL
Output frequency range: 31.25MHz to 630MHz
Input frequency range: 31.25MHz to 630MHz
VCO range: 250MHz to 630MHz
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
External feedback for “zero delay” clock regeneration
with configurable frequencies
Output skew: 50ps (maximum)
Cycle-to-cycle jitter: 35ps (maximum)
Static phase offset: 30ps ± 125ps
3.3V core, 1.8V output operating supply
0°C to 70°C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
Industrial temperature information available upon request
HiPerClockS
ICS
BLOCK DIAGRAM
PIN ASSIGNMENT
ICS8725-21
20-Lead, 300-MIL SOIC
7.5mm x 12.8mm x 2.3mm body package
M Package
Top View
CLK
nCLK
MR
VDD
nFB_IN
FB_IN
SEL2
GND
nQFB
QFB
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nc
SEL1
SEL0
VDD
PLL_SEL
VDDA
SEL3
VDDO
Q
nQ
PLL_SEL
CLK
nCLK
FB_IN
nFB_IN
SEL0
SEL1
SEL2
SEL3
MR
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
Q
nQ
QFB
nQFB
0
1
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
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