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參數(shù)資料
| 型號(hào)： | ICS8705BYT |
| 英文描述： | ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR |
| 中文描述： | 零延遲，DIFFERENTIAL-TO-LVCMOS/LVTTL時(shí)鐘發(fā)生器 |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 293K |
| 代理商： | ICS8705BYT |
8705BY
www.icst.com/products/hiperclocks.html
REV. G JUNE 16, 2004
13
Integrated
Circuit
Systems, Inc.
ICS8705
Z
ERO
D
ELAY
, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
C
LOCK
G
ENERATOR
Other
signals
GND
VDDA
R7
C7
50 Ohm
Trace
C11
VIA
C16
Pin 1
R2
U1
C5
50 Ohm
Trace
VDD
R1
C2
C4
C6
C1
C3
F
IGURE
4B. PCB B
OARD
L
AYOUT
F
OR
ICS8705
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on
the component side is preferred. This can reduce unwanted in-
ductance between the decoupling capacitor and the power pin
caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
DDA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have same
length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The series termination resistors should be located as
close to the driver pins as possible.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS870919BRI-01 | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GENERATOR LVCMOS 28QSOP |
| ICS870919BRI-01LF | 功能描述:IC CLK GENERATOR LVCMOS 28QSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ICS870919BRI-01LFT | 功能描述:IC CLK GENERATOR LVCMOS 28QSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS870919BRI-01T | 制造商:Integrated Device Technology Inc 功能描述:IC CLK GENERATOR LVCMOS 28QSOP |
| ICS870919BRILF | 功能描述:IC CLK GENERATOR LVCMOS 28QSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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