參數(shù)資料
型號: ICS87004AGT
英文描述: 1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL ZERO DELAY CLOCK GENERATOR
中文描述: 1:4,DIFFERENTIAL-TO-LVCMOS/LVTTL零延遲時鐘發(fā)生器
文件頁數(shù): 1/14頁
文件大?。?/td> 185K
代理商: ICS87004AGT
87004AG
www.icst.com/products/hiperclocks.html
REV. A JUNE 16, 2004
1
Integrated
Circuit
Systems, Inc.
ICS87004
1:4, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS87004 is a highly versatile 1:4 Differential-
to-LVCMOS/LVTTL Clock Generator and a mem-
ber of the
HiPerClockS family of High Perfor-
mance Clock Solutions from ICS. The ICS87004
has two selectable clock inputs. The CLK0, nCLK0
and CLK1, nCLK1 pairs can accept most standard differential
input levels. Internal bias on the nCLK0 and nCLK1 inputs
allows the CLK0 and CLK1 inputs to accept LVCMOS/LVTTL.
The ICS87004 has a fully integrated PLL and can be configured
as zero delay buffer, multiplier or divider and has an input and
output frequency range of 15.625MHz to 250MHz. The refer-
ence divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-
input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The exter-
nal feedback allows the device to achieve “zero delay” between
the input clock and the output clocks. The PLL_SEL pin can be
used to bypass the PLL for system test and debug purposes. In
bypass mode, the reference clock is routed around the PLL
and into the internal output dividers.
F
EATURES
4 LVCMOS/LVTTL outputs, 7
typical output impedance
Selectable CLK0, nCLK0 or CLK1, nCLK1 clock inputs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Internal bias on nCLK0 and nCLK1 to support
LVCMOS/LVTTL levels on CLK0 and CLK1 inputs
Output frequency range: 15.625MHz to 250MHz
Input frequency range: 15.625MHz to 250MHz
VCO range: 250MHz to 500MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Fully integrated PLL
Cycle-to-cycle jitter: 45ps (maximum)
Output skew: 45ps (maximum)
Static phase offset: 50 ± 125ps (3.3V ± 5%)
Full 3.3V or 2.5V operating supply
5V tolerant inputs
Lead-Free package available
Industrial temperature information available upon request
P
IN
A
SSIGNMENT
HiPerClockS
ICS
B
LOCK
D
IAGRAM
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
G Package
Top View
PLL_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
SEL0
SEL1
SEL2
SEL3
MR
Q0
Q1
Q2
Q3
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
÷2, ÷4, ÷8, ÷16,
÷32
,
÷64, ÷128
0
1
0
1
GND
Q0
V
DD
o
SEL0
SEL1
SEL2
SEL3
CLK_SEL
V
DD
CLK0
nCLK0
GND
1
2
3
4
5
6
7
8
9
10
11
12
Q1
V
DDO
Q2
GND
Q3
V
DDO
MR
FB_IN
PLL_SEL
CLK1
nCLK1
V
DDA
24
23
22
21
20
19
18
17
16
15
14
13
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