參數(shù)資料
型號: ICS855011AGT
元件分類: 時鐘及定時
英文描述: 855011 SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封裝: 3 MM X 3 MM, 0.95 MM HEIGHT, MO-187, TSSOP-8
文件頁數(shù): 1/10頁
文件大?。?/td> 146K
代理商: ICS855011AGT
855011AG
www.icst.com/products/hiperclocks.html
REV. A MARCH 6, 2006
1
Integrated
Circuit
Systems, Inc.
ICS855011
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-2.5V/3.3V CML FANOUT BUFFER
PRELIMINARY
GENERAL DESCRIPTION
The ICS85 5011 is a low skew, high perfor-
mance 1-to-2 Differential-to-2.5V/3.3V CML
F anout Buff er and a member of the
HiPerClockS family of High Perfor mance
Clock Solutions from ICS. The ICS855011
is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and par t-to-par t skew
characteristics make the ICS85 5011 ideal for those
clock distribution applications demanding well defined
perfor mance and repeatability.
FEATURES
Two differential 2.5V/3.3V CML outputs
One differential PCLK, nPCLK input pair
PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Output frequency: >3GHz
Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
Output skew: 5ps (typical)
Part-to-part skew: TBD
Propagation delay: 242ps (typical)
Operating voltage supply range:
V
CC = 2.375V to 3.8V, VEE = 0V
-40°C to 85°C ambient operating temperature
Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
ICS855011
8-Lead TSSOP
3mm x 3mm x 0.95mm package body
G Package
Top View
Q0
nQ0
Q1
nQ1
1
2
3
4
HiPerClockS
ICS
Vcc
PCLK
nPCLK
VEE
8
7
6
5
Q0
nQ0
Q1
nQ1
PCLK
nPCLK
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
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