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參數(shù)資料
| 型號： | ICS8545BGT |
| 英文描述： | LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER |
| 中文描述： | 低偏移，1至4的LVCMOS / LVTTL至LVDS扇出緩沖器 |
| 文件頁數(shù)： | 12/17頁 |
| 文件大?。?/td> | 252K |
| 代理商： | ICS8545BGT |
12
ICS932S203
0601E—12/22/04
1.
The ICS clock generator is a slave/receiver, SMBus component. It can read back the data stored in the latches
for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol
.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator SMBus interface, the protocol is set to use only "
Block-Writes
" from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop
after any complete byte has been transferred. The Command code and Byte count shown above must be sent,
but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
2.
3.
4.
5.
6.
General SMBus serial interface information
The information in this section assumes familiarity with SMBus programming.
For more information, contact ICS for an SMBus software program.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends a dummy command code
ICS clock will
acknowledge
Controller (host) sends a dummy byte count
ICS clock will
acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will
acknowledge
each byte
one at a time
.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the
byte count
Controller (host) acknowledges
ICS clock sends first byte
(Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host)
Start Bit
Address
D2
(H)
ICS (Slave/Receiver)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
How to Write:
Controller (Host)
Start Bit
Address
D3
(H)
ICS (Slave/Receiver)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Stop Bit
How to Read:
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| ICS83026AMI | LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER |
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| ICS83026AMIT | LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER |
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