參數(shù)資料
型號(hào): ICS8545AG-02
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 8545 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封裝: 6.50 X 4.40 MM, 0.925 MM HEIGHT, MO-153, TSSOP-20
文件頁數(shù): 9/13頁
文件大?。?/td> 1554K
代理商: ICS8545AG-02
ICS8545-02
LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
IDT / ICS LVDS FANOUT BUFFER
5
ICS8545AG-02 REV. A JULY 18, 2007
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 3.3V ± 5%, TA = 0°C to 70°C
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Measured using 50% duty cycle.
Parameter
Symbol
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
350
MHz
tPD
Propagation Delay; NOTE 1
1.0
1.45
ns
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
155.52MHz, Integration Range:
12kHz – 20MHz
0.14
ps
tsk(o)
Output Skew; NOTE 2, 4
60
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 4
450
ps
tR / tF
Output Rise/Fall Time
20% to 80%
150
700
ps
odc
Output Duty Cycle; NOTE 5
≤ 166MHz
45
55
%
> 166MHz
40
60
%
相關(guān)PDF資料
PDF描述
ICS8545AG-02LF 8545 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
ICS8545BGILFT LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 4 INVERTED OUTPUT(S), PDSO20
ICS8545BGILF LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 4 INVERTED OUTPUT(S), PDSO20
ICS8545BGILF 8545 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 4 INVERTED OUTPUT(S), PDSO20
ICS8545BGI 8545 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 4 INVERTED OUTPUT(S), PDSO20
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