參數(shù)資料
型號(hào): ICS8543BGILFT
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 9/18頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK BUFFER MUX 2:4 20-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: HiPerClockS™
類型: 扇出緩沖器(分配),多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 是/是
輸入: CML,HCSL,LVDS,LVHSTL,LVPECL,SSTL
輸出: LVDS
頻率 - 最大: 650MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 帶卷 (TR)
其它名稱: 8543BGILFT
ICS8543 Data Sheet
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
ICS8543BG REVISION E DECEMBER 17, 2010
17
2010 Integrated Device Technology, Inc.
Revision History Sheet
Rev
Table
Page
Description of Change
Date
A
T4E
5
In the VOL row, 1.06 has been moved to the Typical column from the maximum column.
9/18/01
A
3
Updated Figure 1, CLK_EN Timing Diagram.
10/17/01
A
3
Updated Figure 1, CLK_EN Timing Diagram.
11/2/01
A
1
6 - 10
Features section, Bullet 6 to read 3.3V LVDS levels instead of LVPECL.
Updated Parameter Measurement Information figures.
5/6/02
B
T5
5
AC Characteristics table - revised Output Frequency from 650MHz to 800MHz.
6/5/02
C
4E
1
5
Features - deleted bullet "Designed to meet or exceed the requirements of
ANSI TIA/EIA-644".
LVDS Table - changed VOD typical value from 350mV to 280mV.
9/19/02
D
T2
2
4
9
10
11
Pin Characteristics - changed CIN 4pF max. to 4pF typical.
Absolute Maximum Ratings - changed Output rating.
Added Differential Clock Input Interface section.
Added LVPECL Clock Input Interface section.
Added LVDS Driver Termination section.
Updated format throughout data sheet.
12/31/03
D
T1
2
Pin Description table - added function description to the OE pin.
4/7/04
D
T8
10
13
Updated LVPECL Clock Input Interface section.
Added Lead Free part number to Ordering Information table.
6/16/04
D
3
10
11
12
13
Updated Figure 1, CLK_EN Timing Diagram.
Updated Differential Clock Input Interface section.
Updated LVPECL Clock Input Interface section.
Added Recommendation for Unused Input and Output Pins section.
Added Power Considerations section.
Updated format throughout the datasheet.
2/27/08
E
T5
T9
1
6
7
10
11
12
13
16
Features section - added Additive Phase Jitter bullet.
AC Characteristics Table - added Added Phase Jitter spec and thermal note.
Added Additive Phase Jitter plot.
Updated Wiring the Differential Input to Accept Single-ended Levels section.
Updated 3.3V Differential Clock Input Interface section.
Updated 3.3V LVPECL Clock Input Interface section.
Updated LVDS Driver Termination section.
Ordering Information Table - deleted “ICS” prefix from Part/Order Number column.
Updated datasheet header/footer style.
11/12/10
E
1
14
Page 1, corrected Header Title.
Power Considerations - corrected typo for junction temperature from 827.7°C to 82.7°C.
12/17/10
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