參數(shù)資料
型號(hào): ICS854058AGT
元件分類: 編、解碼器及復(fù)用、解復(fù)用
英文描述: 8 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO24
封裝: 4.40 X 7.80 MM, 0.92 MM HEIGHT, MS-153, TSSOP-24
文件頁數(shù): 12/12頁
文件大小: 174K
代理商: ICS854058AGT
854058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 8, 2004
9
Integrated
Circuit
Systems, Inc.
ICS854058
8:1
DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER
PRELIMINARY
SCHEMATIC EXAMPLE
An application schematic example of ICS854058 is shown
in
Figure 4. The inputs can accept various types of differential
signals. In this example, the inputs are driven by LVDS drivers.
The transmission lines are assumed to be 100
differential.
The 100
matched loads termination should be located
near the receivers. It is recommended at least one
decoupling capacitor per power pin. The decoupling ca-
pacitor should be low ESR and located as close as pos-
sible to the power pin.
FIGURE 4. ICS854058 SCHEMATIC EXAMPLE
R1
100
100 Ohm Differential
Zo = 50
3.3V
VDD
U1
ICS854058
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
24
23
22
21
PCLK0
nPCLK0
PCLK1
nPCLK1
VDD
SEL0
SEL1
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
nPCLK4
PCLK4
nPCLK5
PCLK5
GND
nQ0
Q0
VDD
PCLK7
nPCLK7
PCLK6
nPCLK6
C2
0.1u
Zo = 50
3.3V
RU1
1K
Set Logic
Input to
'0'
C1
0.1u
LVDS
+
-
To Logic
Input
pins
100 Ohm Dif ferential
RD1
Not Install
To Logic
Input
pins
R3
100
LVDS
Logic Control Input Examples
LVDS
Set Logic
Input to
'1'
Zo = 50
R2
100
RD2
1K
Zo = 50
VDD
Zo = 50
100 Ohm Differential
RU2
Not Install
Zo = 50
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