參數(shù)資料
型號(hào): ICS8534AY-01T
英文描述: LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
中文描述: 低偏移,1至22差分至3.3伏的LVPECL扇出緩沖器
文件頁(yè)數(shù): 8/17頁(yè)
文件大?。?/td> 247K
代理商: ICS8534AY-01T
8534AY-01
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 19, 2004
8
Integrated
Circuit
Systems, Inc.
ICS8534-01
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
Figure 2shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
2. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
R2
1K
V
CC
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
V
CC
- 2V
50
50
RTT
Z
o
= 50
Z
o
= 50
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125
125
84
84
Z
o
= 50
Z
o
= 50
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50
transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
F
IGURE
3B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
3A. LVPECL O
UTPUT
T
ERMINATION
T
ERMINATION
FOR
3.3V LVPECL O
UTPUTS
相關(guān)PDF資料
PDF描述
ICS85354AK DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
ICS85354AKT DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
ICS85354 DUAL 2:1/1:2 DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
ICS85356 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER
ICS85356AMI 2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER
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