參數(shù)資料
型號: ICS853310AV
元件分類: 時鐘及定時
英文描述: 853310 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28
封裝: 11.60 X 11.40 MM, 4.10 MM HEIGHT, PLASTIC, MS-018, LCC-28
文件頁數(shù): 2/16頁
文件大?。?/td> 209K
代理商: ICS853310AV
853310AV
www.icst.com/products/hiperclocks.html
REV. A NOVEMBER 22, 2005
10
Integrated
Circuit
Systems, Inc.
ICS853310
LOW SKEW, 1-TO-8
DIFFERENTIAL-TO-3.3V LVPECL/ECL FANOUT BUFFER
POWER, GROUND AND BYPASS CAPACITOR
This section provides a layout guide related to power, ground
and placement of bypass capacitors for a high-speed digital IC.
This layout guide is a general recommendation.The actual board
design will depend on the component types being used, the board
density and cost constraints. This description assumes that the
board has clean power and ground planes. The goal is to mini-
mize the ESR between the clean power/ground plane and the IC
power/ground pin.
A low ESR bypass capacitor should be used on each power pin.
The value of bypass capacitors ranges from 0.01uF to 0.1uF.
The bypass capacitors should be located as close to the power
GND
IC
Power pin
GND Pin
Via
GND Pad
C
Power Pad
FIGURE 4B. RECOMMENDED LAYOUT OF BYPASS CAPACITOR PLACEMENT
pin as possible. It is preferable to locate the bypass capacitor on
the same side as the IC. Figure 4B shows suggested capacitor
placement. Placing the bypass capacitor on the same side as
the IC allows the capacitor to have direct contact with the IC
power pin. This can avoid any vias between the bypass capaci-
tor and the IC power pins.
The vias should be placed at the Power/Ground pads.There should
be a minimum of one via per pin. Increasing the number of vias
from the Power/Ground pads to Power/Ground planes can im-
prove the conductivity.
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