參數(shù)資料
型號(hào): ICS85211AMT
元件分類: 時(shí)鐘及定時(shí)
英文描述: LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封裝: 3.90 X 4.90 MM, 1.37 MM HEIGHT, SOIC-8
文件頁(yè)數(shù): 7/11頁(yè)
文件大小: 133K
代理商: ICS85211AMT
85211AM
www.icst.com/products/hiperclocks.html
REV. A JANUARY 3, 2003
5
Integrated
Circuit
Systems, Inc.
ICS85211
LOW SKEW, 1-TO-2
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
PRELIMINARY
SCHEMATIC EXAMPLE
Figure 2 shows a schematic example of ICS85211. In this
example, the input is driven by an ICS HiPerClockS LVHSTL
driver. The decoupling capacitors should be physically located
FIGURE 2. ICS85211 LVHSTL BUFFER SCHEMATIC EXAMPLE
Zo = 50 Ohm
R1
50
R5
50
HiPerClockS
R6
50
LVHSTL
LVHSTL Input
+
-
Zo = 50 Ohm
R3
50
Zo = 50 Ohm
LVHSTL Input
+
-
R4
50
1.8V
Zo = 50 Ohm
C1
0.1u
ICS
R2
50
U1
ICS85211-03
1
2
3
4
8
7
6
5
Q0
nQ0
Q1
nQ1
VDD
CLK
nCLK
GND
VDD=3.3V
LVHSTL Driver
near the power pin. For ICS85211, the unused outputs need
to be terminated.
APPLICATION INFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
R2
1K
V
DD
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
相關(guān)PDF資料
PDF描述
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