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參數(shù)資料
| 型號(hào)： | ICS85105AGILFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 85105 SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | 6.50 MM X 4.40 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-20 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 656K |
| 代理商： | ICS85105AGILFT |
LOW SKEW, 1-TO-5, DIFFERENTIAL/
LVCMOS-TO-0.7V HCSL FANOUT BUFFER
ICS85105I
IDT / ICS 0.7V HCSL FANOUT BUFFER
1
ICS85105AGI REV. A NOVEMBER 10, 2006
PRELIMINARY
GENERAL DESCRIPTION
The ICS85105I is a low skew, high performance 1-
to-5 Differential-to-0.7V HCSL Fanout Buffer and
a member of the HiPerClockS family of High
Perfo r mance Clock Solutions from IDT. The
ICS85105I has two selectable clock inputs. The
CLK0, nCLK0 pair can accept most standard differential
input levels. The single-ended CLK1 can accept LVCMOS or
LVTTL input levels. The clock enable is internally synchronized
to eliminate runt clock pulses on the outputs during asynchro-
nous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make
the ICS85105I ideal for those applications demanding well
defined performance and repeatability.
FEATURES
Five 0.7V differential HCSL outputs
Selectable differential CLK0, nCLK0 or LVCMOS inputs
CLK0, nCLK0 pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 500MHz
Translates any single-ended input signal to 3.3V
HCSL levels with resistor bias on nCLK input
Output skew: 75ps (typical), TSSOP package
TBD, SOIC package
Part-to-part skew: 300ps (typical)
Propagation delay: 2.4ns (typical)
Additive phase jitter, RMS: 0.31ps (typical)
3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
HiPerClockS
ICS
BLOCK DIAGRAM
PIN ASSIGNMENT
VSS
CLK_EN
CLK_SEL
CLK0
nCLK0
CLK1
Q4
nQ4
IREF
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
VDD
Q1
nQ1
Q2
nQ2
VDD
Q3
nQ3
ICS85105I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm Package Body
G Package
Top View
ICS85105I
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm Package Body
M Package
Top View
Q0
nQ0
Q1
nQ1
CLK_EN
CLK_SEL
IREF
CLK1
CLK0
nCLK0
D
LE
Q
0
1
Q2
nQ2
Q4
nQ4
Q3
nQ3
Pulldown
Pullup
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization and/
or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS85105AGIT | 制造商:Integrated Device Technology Inc 功能描述:IC CLK BUFFER 2:5 500MHZ 20TSSOP |
| ICS85108AGI | 制造商:Integrated Device Technology Inc 功能描述:IC CLK BUFFER 1:8 500MHZ 24TSSOP |
| ICS85108AGILF | 功能描述:IC CLK BUFFER 1:8 500MHZ 24TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:HiPerClockS™ 產(chǎn)品培訓(xùn)模塊:High Bandwidth Product Overview 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:4 差分 - 輸入:輸出:是/是 輸入:CML，LVDS，LVPECL 輸出:CML 頻率 - 最大:2.5GHz 電源電壓:2.375 V ~ 2.625 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) |
| ICS85108AGILFT | 功能描述:IC CLK BUFFER 1:8 500MHZ 24TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘緩沖器，驅(qū)動(dòng)器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:管件 |
| ICS85108AGIT | 制造商:Integrated Device Technology Inc 功能描述:IC CLK BUFFER 1:8 500MHZ 24TSSOP |
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