參數(shù)資料
型號(hào): ICS844003BGI-01LFT
元件分類(lèi): 時(shí)鐘產(chǎn)生/分配
英文描述: 680 MHz, OTHER CLOCK GENERATOR, PDSO24
封裝: 4.40 X 7.80 MM, 0.92MM HEIGHT, ROHS COMPLIANT, TSSOP-24
文件頁(yè)數(shù): 2/15頁(yè)
文件大?。?/td> 763K
代理商: ICS844003BGI-01LFT
844003BGI-0I
www.icst.com/products/hiperclocks.html
REV. A MARCH 28, 2006
10
Integrated
Circuit
Systems, Inc.
ICS844003BI-01
FEMTOCLOCKS CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
PRELIMINARY
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating.
Though not required, but for additional protection, a 1k
Ω
resistor can be tied from XTAL_IN to ground.
REF_CLK INPUT:
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1k
Ω resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVDS
All unused LVDS output pairs can be either left floating or
terminated with 100
Ω across. If they are left floating, we
recommend that there is no trace attached.
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS
signal through an AC couple capacitor. A general interface
diagram is shown in Figure 3. The XTAL_OUT pin can
be left floating. The input edge rate can be as slow as
10ns. For LVCMOS inputs, it is recommended that the
amplitude be reduced from full swing to half swing in order
to prevent signal interference with the power rail and to
reduce noise. This configuration requires that the output
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
impedance of the driver (Ro) plus the series resistance
(Rs) equals the transmission line impedance. In addition,
matched termination at the crystal input will attenuate the
signal in half. This can be done in one of two ways. First,
R1 and R2 in parallel should equal the transmission line
impedance. For most 50
Ω applications, R1 and R2 can be
100
Ω. This can also be accomplished by removing R1 and
making R2 50
Ω.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL_IN
XTAL_OUT
.1uf
Rs
相關(guān)PDF資料
PDF描述
ICS844003BGI-01LF 680 MHz, OTHER CLOCK GENERATOR, PDSO24
ICS844003BGI-01LF 680 MHz, OTHER CLOCK GENERATOR, PDSO24
ICS844003CG-01LFT 680 MHz, OTHER CLOCK GENERATOR, PDSO24
ICS844004AGI-01 156.5 MHz, OTHER CLOCK GENERATOR, PDSO24
ICS844004AGI-01LFT 156.5 MHz, OTHER CLOCK GENERATOR, PDSO24
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