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參數(shù)資料
| 型號： | ICS84330CM-01LF |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 700 MHz, OTHER CLOCK GENERATOR, PDSO28 |
| 封裝： | 7.50 X 18.05 MM, 2.25 MM HEIGHT, MS-013, MO-119, SOIC-28 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大小： | 240K |
| 代理商： | ICS84330CM-01LF |
84330CV-01
www.icst.com/products/hiperclocks.html
REV. B MARCH 22, 2004
2
Integrated
Circuit
Systems, Inc.
ICS84330-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
N0 through N1 is passed directly to the M divider and N output
divider. On the LOW-to-HIGH transition of the nP_LOAD input,
the data is latched and the M divider remains loaded until the
next LOW transition on nP_LOAD or until a serial event occurs.
The TEST output is Mode 000 (shift register out) when operat-
ing in the parallel input mode. The relationship between the VCO
frequency, the crystal frequency and the M divider is defined as
follows:
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock are
defined as 100
≤ M ≤ 350. The frequency out is defined as
follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider when S_LOAD transitions
from LOW-to-HIGH. The M divide and N output divide values
are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed di-
rectly to the M divider on each rising edge of S_CLOCK. The
serial mode can be used to program the M and N bits and test
bits T2:T0. The internal registers T2:T0 determine the state of
the TEST output as follows:
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
for different crystal or input frequencies are defined in the In-
put Frequency Characteristics, Table 6, NOTE 1.
The ICS84330-01 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A quartz crystal is used as the input to the on-chip
oscillator. The output of the oscillator is divided by 16 prior to
the phase detector. With a 16MHz crystal this provides a 1MHz
reference frequency. The VCO of the PLL operates over a
range of 200MHz to 700MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output fre-
quency to be 2M times the reference frequency divided by 16
by adjusting the VCO control voltage. Note that for some values
of M (either too high or too low), the PLL will not achieve lock.
The output of the VCO is scaled by a divider prior to being sent
to each of the LVPECL output buffers. The divider provides a
50% output duty cycle.
The programmable features of the ICS84330-01 support two
input modes to program the M divider and N output divider. The
two input operational modes are parallel and serial.
Figure 1
shows the timing diagram for each mode. In parallel mode the
nP_LOAD input is LOW. The data on inputs M0 through M8 and
Time
SERIAL LOADING
PARALLEL LOADING
M, N
t
S
t
H
t
S
t
H
t
S
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
16
2M
fVCO =
fxtal x
N
fout =
fVCO
=
16
2M
fxtal x
N
T2
T1
T0
TEST Output
0
Shift Register Out
0
1
High
0
1
0
PLL Reference Xtal ÷ 16
0
1
(VCO ÷ M) /2 (non 50% Duty M divider)
1
0
fOUT
LVCMOS Output Frequency < 200MHz
1
0
1
Low
1
0
(S_CLOCK ÷ M) /2 (non 50% Duty Cycle M divider)
1
fOUT ÷ 4
fOUT
fOUT
S_CLOCK ÷ N divider
fOUT
T2
T1
T0
N 1
N 0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS84330CM-01LFT | 功能描述:IC FREQ SYNTHESIZER 28SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS84330CM-01T | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS84330CV | 制造商:Integrated Device Technology Inc 功能描述:IC SYNTHESIZER 700MHZ 28-PLCC |
| ICS84330CV-01 | 制造商:Integrated Device Technology Inc 功能描述:IC SYNTHESIZER 700MHZ 28-PLCC |
| ICS84330CV-01LF | 功能描述:IC SYNTHESIZER 700MHZ 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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