700MHZ, L
參數(shù)資料
型號(hào): ICS84330AV-02LFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 19/19頁
文件大小: 0K
描述: IC SYNTHESIZER 700MHZ 28-PLCC
標(biāo)準(zhǔn)包裝: 500
系列: HiPerClockS™
類型: 頻率合成器
PLL:
輸入: LVCMOS,LVTTL,晶體
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 無/是
頻率 - 最大: 700MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 28-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 28-PLCC(11.5x11.5)
包裝: 帶卷 (TR)
其它名稱: 84330AV-02LFT
84330AV-02
www.idt.com
REV. B JULY 25, 2010
9
ICS84330-02
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
50
40
30
20
10
0
200
300
600
700
400
500
Output Frequency (MHz)
Cyc
le-to-Cyc
le
Jitter
(ps)
N = 1
Spec Limit
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept single ended LVCMOS signal
through an AC couple capacitor. A general interface diagram
is shown in Figure 4. The XTAL_OUT input can be left floating.
The edge rate can be as slow as 10ns. If the incoming signal
has sharp edge rate and the signal path is a long trace, proper
termination for the driver and controlled characteristic imped-
Figure 4. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
ance trace may be required. The input can function with half
swing amplitude. Reducing amplitude from full swing of 3.3V
to half swing of about 1.65V can prevent signal interfere with
power rail and may reduce noise. Please refer to the LVCMOS
driver data sheet and application note for amplitude reduction
and termination approach.
FIGURE 5. CYCLE-TO-CYCLE JITTER VS. fOUT (using a 16MHz XTAL)
Cry stal Interf ace
XTAL_IN
XTAL_OUT
C1
0.1uF
LVCMOS_Driv er
3.3V
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