參數(shù)資料
型號(hào)： ICS8432CYI-01T
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 700 MHz, OTHER CLOCK GENERATOR, PQFP32
封裝： 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
文件頁(yè)數(shù)： 3/17頁(yè)
文件大?。?/td> 174K
代理商： ICS8432CYI-01T
8432CYI-01
www.icst.com/products/hiperclocks.html
REV. D SEPTEMBER 6, 2001
11
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-01I
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
FIGURE 10B. LVPECL OUTPUT TERMINATION
3.3V
F
OUT
F
IN
5
2 Zo
Z
o
5
2
Z
o
3
2
Z
o
3
2
Z
o = 50
Z
o = 50
Z
o = 50
Z
o = 50
FIGURE 10A. LVPECL OUTPUT TERMINATION
RTT =
1
(V
OH + VOL / VCC –2) –2
Z
o
Z
o = 50
Z
o = 50
50
50
RTT
V
CC - 2V
F
IN
F
OUT
Z
o = 50
Z
o = 50
drive 50
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and mini-
mize signal distortion. There are a few simple termination
schemes.
Figures 10A and 10B show two different layouts
which are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended that
the board designers simulate to guarantee compatibility across
all printed circuit and clock component process variations.
TERMINATION FOR LVPECL OUTPUTS
The schematic of the ICS8432-01I layout example used in this layout guideline is shown in
Figure 11A. The ICS8432-01I recom-
mended PCB board layout for this example is shown in
Figure 11B. This layout example is used as a general guideline. The layout in
the actual system will depend on the selected component types, the density of the components, the density of the traces, and the
stacking of the P.C. board.
LAYOUT GUIDELINE
XTAL_SEL
VCC
Termination A
REF_IN
MR
X1
FO
UTN
IN-
R7
10
R2
84
R3
125
IN-
R1
125
S_CLOCK
IN+
C14
0.1u
FO
UT
TEST
TL1
Zo = 50 Ohm
S_DATA
Termination
B (Not shown
in the layout)
C16
10u
R3
50
S_LOAD
VCC
C15
0.1u
R4
84
C11
0.01u
R2
50
R1
50
IN+
TL2
Zo = 50 Ohm
VCC
U1
8432-01
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
M5
M6
M7
M8
N0
N1
nc
VEE
TEST
VCC
FO
UT1
nF
O
U
T
1
VCCO
FO
UT0
nF
O
U
T
0
VEE
MR
S_CLOCK
S_DATA
S_LOAD
VCCA
nXTAL_SEL
REF_IN
XTAL1
M4
M3
M2
M1
M0
VCO_
SEL
nP
_LO
A
D
XTAL
2
FIGURE 11A. RECOMMENDED SCHEMATIC LAYOUT
相關(guān)PDF資料
PDF描述
ICS8432DY-101LFT 8432 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
ICS8432DY-101T 8432 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
ICS8432DY-101LF 8432 SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
ICS8432DYI-01 700 MHz, OTHER CLOCK GENERATOR, PQFP32
ICS8432DYI-01LF 700 MHz, OTHER CLOCK GENERATOR, PQFP32
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS8432DI-101 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICS8432DY101 制造商:ICS 功能描述:
ICS8432DY-101 制造商:ICS 功能描述:
ICS8432DY-101LF 功能描述:IC SYNTHESIZER 700MHZ 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR
ICS8432DY-101LFT 功能描述:IC SYNTHESIZER 700MHZ 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT
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