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參數(shù)資料
| 型號： | ICS8432CY-11 |
| 英文描述： | 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER |
| 中文描述： | 700MHZ/350MHZ，低相位噪聲，晶體至3.3的LVPECL頻率合成器 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 187K |
| 代理商： | ICS8432CY-11 |
8432CY-11
www.icst.com/products/hiperclocks.html
REV. E MAY 20, 2005
2
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8432-11
700MH
Z
/350MH
Z
, L
OW
P
HASE
N
OISE
,
C
RYSTAL
-
TO
- 3.3V LVPECL F
REQUENCY
S
YNTHESIZER
nP_LOAD or until a serial event occurs. As a result, the M and
N bits can be hardwired to set the M divider and N output divider
to a specific default state that will automatically occur during
power-up. The TEST output is LOW when operating in the paral-
lel input mode. The relationship between the VCO frequency,
the input frequency and the M divider is defined as follows:
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock are
defined as 8
≤
M
≤
28. The frequency out is defined as follows:
fOUT = fVCO = fxtal x M
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider and N output
divider when S_LOAD transitions from LOW-to-HIGH. The
M divide and N output divide values are latched on the HIGH-
to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data
at the S_DATA input is passed directly to the M divider and
N output divider on each rising edge of S_CLOCK. The serial
mode can be used to program the M and N bits and test bits
T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
T1
T0
TEST Output
Time
S
ERIAL
L
OADING
P
ARALLEL
L
OADING
M, N
F
UNCTIONAL
D
ESCRIPTION
NOTE: The functional description that follows describes
operation using a 25MHz clock input. Valid PLL loop divider
values for different input frequencies are defined in the Input
Frequency Characteristics, Table 5, NOTE 1.
The ICS8432-11 features a fully integrated PLL and there-
fore requires no external components for setting the loop
bandwidth. A differential clock input is used as the input to the
ICS8432-11. This input is fed into the phase detector. A 25MHz
clock input provides a 25MHz phase detector reference fre-
quency. The VCO of the PLL operates over a range of 200MHz
to 700MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjust-
ing the VCO control voltage. Note, that for some values of M
(either too high or too low), the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent
to each of the LVPECL output buffers. The divider provides
a 50% output duty cycle.
The programmable features of the ICS8432-11 support two
input modes to program the PLL M divider and N output
divider. The two input operational modes are parallel and
serial. Figure1 shows the timing diagram for each mode. In
parallel mode, the nP_LOAD input is initially LOW. The data
on inputs M0 through M8 and N0 and N1 is passed directly
to the M divider and N output divider. On the LOW-to-HIGH
transition of the nP_LOAD input, the data is latched and the
M divider remains loaded until the next LOW transition on
fVCO = fxtal x M
0
0
LOW
0
1
S_Data, Shift Register Input
1
0
Output of M divider
1
1
CMOS Fout/2
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
*
NOTE:
The NULL timing slot must be observed.
T1
T0
*
NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
S_LOAD
N
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS8432CY111 | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8432CY-111 | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS8432CY-111LF | 功能描述:IC SYNTHESIZER 700/350MHZ 32LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS8432CY-111LFT | 功能描述:IC SYNTHESIZER 700/350MHZ 32LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS8432CY-111T | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ/350MHZ DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
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