- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2073 > ICS84329BM-01LF (IDT, Integrated Device Technology Inc)IC SYNTHESIZER 700MHZ 28-SOIC PDF資料下載
參數(shù)資料
| 型號： | ICS84329BM-01LF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 12/21頁 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER 700MHZ 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 26 |
| 系列： | HiPerClockS™ |
| 類型： | 頻率合成器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 700MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC |
| 包裝： | 管件 |
| 其它名稱： | 84329BM-01LF |
ICS84329B-01
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
IDT / ICS LVPECL FREQUENCY SYNTHESIZER
2
ICS84329BM-01 REV. C AUGUST 19, 2013
Functional Description
NOTE: The functional description that follows describes operation
using a 16MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 6, NOTE 1.
The ICS84329B-01 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth. A
parallel resonant, fundamental crystal is used as the input to the
on-chip oscillator. The output of the oscillator is divided by 16 prior
to the phase detector. With a 16MHz crystal this provides a 1MHz
reference frequency. The VCO of the PLL operates over a range
of 250MHz to 700MHz. The output of the M divider is also applied
to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency ÷ 16 by adjusting
the VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the
LVPECL output buffers. The divider provides a 50% output duty
cycle.
The programmable features of the ICS84329B-01 support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial. Figure 1
shows the timing diagram for each mode. In parallel mode the
nP_LOAD input is LOW. The data on inputs M0 through M8 and N0
through N1 is passed directly to the M divider and N output divider.
On the LOW-to-HIGH transition of the nP_LOAD input, the data is
latched and the M divider remains loaded until the next LOW
transition on nP_LOAD or until a serial event occurs. The TEST
output is Mode 000 (shift register out) when operating in the
parallel input mode. The relationship between the VCO frequency,
the crystal frequency and the M divider is defined as follows:
fVCO = fXTAL x M
16
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock are defined as
250
M 511. The frequency out is defined as follows:
fout = fVCO = fXTAL x M
N16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider when S_LOAD transitions from
LOW-to-HIGH. The M divide and N output divide values are
latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is
held HIGH, data at the S_DATA input is passed directly to the M
divider on each rising edge of S_CLOCK. The serial mode can be
used to program the M and N bits and test bits T2:T0. The internal
resistors T2:T0 determine the state of the TEST output as follows:
T2
T1
T0
TEST Output
fOUT
0
Shift Register Out
fOUT
00
1
HIGH
fOUT
0
1
0
PLL Reference XTAL ÷16
fOUT
0
1
(VCO ÷ M) /2 (non 50% Duty Cycle M Divider)
fOUT
1
0
fOUT, LVCMOS Output Frequency < 200MHz
fOUT
10
1
LOW
fOUT
1
0
S_CLOCK ÷ M (non 50% Duty Cycle M Divider)
S_CLOCK ÷ N Divider
1
fOUT ÷ 4
fOUT
Time
SERIAL LOADING
PARALLEL LOADING
t
S
t
H
t
S
t
H
t
S
M, N
M0
M1
M2
M3
M4
M5
M6
M7
M8
N0
N1
T0
T1
T2
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, N0:N1
nP_LOAD
Figure 1. Parallel & Serial Load Operations
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS84330AV-02LF | IC SYNTHESIZER 700MHZ 28-PLCC |
| ICS84330CM-01LF | IC FREQ SYNTHESIZER 28SOIC |
| ICS843321AGI-12LF | IC SYNTHESIZER CLK SONET 8TSSOP |
| ICS843S1333DGLF | IC CLK SYNTHESIZER 8TSSOP |
| ICS844003BG-01LF | IC SYNTHESIZER 3LVDS 24-ETSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS84329BM-01LFT | 功能描述:IC SYNTHESIZER 700MHZ 28-SOIC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS84329BM-01T | 制造商:Integrated Device Technology Inc 功能描述:IC SYNTHESIZER 700MHZ 28-SOIC |
| ICS84329BV | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| ICS84329BV-01 | 制造商:Integrated Device Technology Inc 功能描述:IC SYNTHESIZER 700MHZ 28-PLCC |
| ICS84329BV-01LF | 功能描述:IC SYNTHESIZER 700MHZ 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。