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參數(shù)資料
| 型號(hào)： | ICS84326 |
| 英文描述： | CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER |
| 中文描述： | 水晶到3.3的LVPECL串行連接SCSI時(shí)鐘合成器/扇出緩沖器 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 171K |
| 代理商： | ICS84326 |
84326AM
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2003
10
ICS84326
C
RYSTAL
-
TO
-3.3V LVPECL
S
ERIAL
A
TTACHED
SCSI C
LOCK
S
YNTHESIZER
/F
ANOUT
B
UFFER
PRELIMINARY
ICS84326
R7
VIA
C1
VCC
GND
C11
C2
C16
U1
C5
Pin1
X1
C6
50 Ohm Traces
C3
Signals
F
IGURE
5B. ICS84326 P.C. B
OARD
L
AYOUT
E
XAMPLE
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C5, C6 and C3, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
CCA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have the
same length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
C
RYSTAL
The crystal X1 should be located as close as possible to the pins
20 (XTAL1) and 19 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS84326AM | 制造商:ICS 制造商全稱:ICS 功能描述:CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER |
| ICS84326AMT | 制造商:ICS 制造商全稱:ICS 功能描述:CRYSTAL-TO-3.3V LVPECL SERIAL ATTACHED SCSI CLOCK SYNTHESIZER/FANOUT BUFFER |
| ICS84327 | 制造商:ICS 制造商全稱:ICS 功能描述:CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER |
| ICS84327AM | 制造商:ICS 制造商全稱:ICS 功能描述:CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER |
| ICS84327AMLF | 功能描述:IC SYNTHESIZER LVPECL 24SOIC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:HiPerClockS™ 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
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