IDT / ICS 3.3V, 2.5V LVPECL CLOCK GENERATOR
8
ICS843251BGI-12 REV. A NOVEMBER 19, 2012
ICS843251I-12
FEMTOCLOCK
CRYSTAL-TO-3.3V, 2.5V LVPECL CLOCK GENERATOR
TERMINATION FOR 3.3V LVPECL OUTPUTS
V
CC - 2V
50
Ω
50
Ω
RTT
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o = 50Ω
Z
o = 50Ω
FOUT
FIN
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
FIGURE 4B. LVPECL OUTPUT TERMINATION
FIGURE 4A. LVPECL OUTPUT TERMINATION
designed to dr ive 50
Ω transmission lines. Matched imped-
ance techniques should be used to maximize operating fre-
quency and minimize signal distor tion.
Figures 4A and 4B
show two different layouts which are recommended only as
guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.