IDT / ICS 3.3V LVPECL FREQUENCY SYNTHESIZ" />
參數(shù)資料
型號: ICS843204AGILFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 15/16頁
文件大?。?/td> 0K
描述: IC SYNTHESIZER LVPECL 48-TSSOP
標(biāo)準(zhǔn)包裝: 1,000
系列: HiPerClockS™, FemtoClock™
類型: 頻率合成器
PLL:
輸入: LVCMOS,LVTTL,晶體
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 4:4
差分 - 輸入:輸出: 無/是
頻率 - 最大: 156.25MHz
除法器/乘法器: 是/無
電源電壓: 2.97 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 帶卷 (TR)
其它名稱: 843204AGILFT
IDT / ICS 3.3V LVPECL FREQUENCY SYNTHESIZER
8
ICS843204AGI REV. A MARCH 18, 2009
ICS843204I
FEMTOCLOCK CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in
Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS signals, it
is recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50
Ω applications, R1
and R2 can be 100
Ω. This can also be accomplished by removing
R1 and making R2 50
Ω.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL_IN
XTAL_OUT
.1uf
Rs
CRYSTAL INPUT INTERFACE
The ICS843204I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in
Figure 2 below
FIGURE 2. CRYSTAL INPUT INTERFACE
were determined using an 18pF parallel resonant crystal and
were chosen to minimize the ppm error.
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
27p
C2
27p
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