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參數(shù)資料
| 型號： | ICS84320-01K |
| 英文描述： | 780MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| 中文描述： | 支持780MHZ，水晶到3.3V的差分LVPECL頻率合成器 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 386K |
| 代理商： | ICS84320-01K |
84320AK-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 6, 2004
11
Integrated
Circuit
Systems, Inc.
ICS84320-01K
780MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
PRELIMINARY
F
IGURE
5B. PCB B
OARD
L
AYOUT
FOR
ICS84320-01K
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C14 and C15, as close as pos-
sible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
CCA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have the
same length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
C
RYSTAL
The crystal X1 should be located as close as possible to the pins
25 (XTAL1) and 24 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
TL1, TL21N are 50 Ohm
traces and equal length
R2
VIA
T
GND
C15
R4
TL1
R1
T
X1
VCC
C11
PIN 1
C1
C14
TL1N
C2
R3
C16
R7
Close to the input
pins of the
receiver
U1
VCCA
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