參數(shù)資料
型號(hào): ICS8431EMI-01
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 200 MHz, OTHER CLOCK GENERATOR, PDSO28
封裝: 7.50 X 18.05 MM, 2.25 MM, MS-013, MO-119, SOIC-28
文件頁數(shù): 1/15頁
文件大?。?/td> 328K
代理商: ICS8431EMI-01
8431EMI-01
www.icst.com/products/hiperclocks.html
REV. A FEBRUARY 4, 2003
1
Integrated
Circuit
Systems, Inc.
ICS8431I-01
200MHZ, LOW JITTER,
CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
XTAL1
XTAL2
SSC_CTL0
SSC_CTL1
GENERAL DESCRIPTION
The ICS8431I-01 is a general purpose clock
frequency synthesizer for IA64/32 applications
and a member of the HiPerClockS family of High
Performance Clock Solutions from ICS. The
ICS8431I-01 consists of one independent low
bandwidth PLL timing channel. A 16.666MHz crystal is used
as the input to the on-chip oscillator. The M divide is config-
ured to produce a fixed output frequency of 200MHz.
Programmable features of the ICS8431I-01 support four
operational modes. The four modes are spread spectrum
clocking (SSC), non-spread spectrum clocking and two test
modes which are controlled by the SSC_CTL[1:0] pins. Un-
like other synthesizers, the ICS8431I-01 can immediately
change spread-spectrum operation without having to reset
the device.
In SSC mode, the output clock is modulated in order to
achieve a reduction in EMI. In one of the PLL bypass test
modes, the PLL is disconnected as the source to the
differential output allowing an external source to be
connnected to the TEST_I/O pin. This is useful for in-
circuit testing and allows the differential output to be driven
at a lower frequency throughout the system clock tree. In the
other PLL bypass mode, the oscillator divider is used as the
source to both the M divide and the Fout divide by 2. This is
useful for characterizing the oscillator and internal dividers.
BLOCK DIAGRAM
PIN ASSIGNMENT
FEATURES
Fully integrated PLL
Differential 3.3V LVPECL output
Crystal oscillator interface
Output frequency of 200MHz
48% to 52% duty cycle
Spread Spectrum Clocking (SSC) fixed at 1/
2% modulation
for environments requiring ultra low EMI. Typical10dB EMI
reduction can be achieved with spread spectrum modulation
PLL bypass modes supporting in-circuit testing and on-chip
functional block characterization
Cycle-to-cycle jitter: 25ps (maximum)
3.3V supply voltage
-40° to 85°C ambient operating temperature
PLL
FOUT
nFOUT
÷ 16
nc
SSC_CTL0
SSC_CTL1
VEE
TEST_I/O
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nc
VCC
XTAL2
XTAL1
nc
VCCA
VEE
RESERVED
nc
VCCO
FOUT
nFOUT
VEE
ICS8431I-01
28-Lead SOIC
7.5mm x 18.05mm x 2.25mm package body
M Package
Top View
TEST_I/O
OSC
VCO
÷ 2
PHASE
DETECTOR
÷ M
SSC
Control
Logic
HiPerClockS
,&6
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