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參數資料
| 型號： | ICS8431AMI-21T |
| 英文描述： | 350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| 中文描述： | 350MHz頻段，低抖動，晶體振蕩器到3.3的LVPECL頻率合成器 |
| 文件頁數： | 8/16頁 |
| 文件大?。?/td> | 207K |
| 代理商： | ICS8431AMI-21T |
8431AMI-21
www.icst.com/products/hiperclocks.html
REV. A AUGUST 2, 2005
8
Integrated
Circuit
Systems, Inc.
ICS8431I-21
350MH
Z
, L
OW
J
ITTER
, C
RYSTAL
O
SCILLATOR
-
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8431I-21 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. V
, V
, and V
should
be individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, better power supply iso-
lation is required. Figure 3 llustrates how a 10
Ω
along with a
10
μ
F and a .01
μ
F bypass capacitor should be connected to
each V
CCA
pin.
F
IGURE
3. P
OWER
S
UPPLY
F
ILTERING
10
Ω
V
CCA
10
μ
F
.01
μ
F
3.3V
.01
μ
F
V
CC
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
A
PPLICATION
I
NFORMATION
The clock layout topology shown below is typical for
IA64/32 platforms. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
F
IGURE
2B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
2A. LVPECL O
UTPUT
T
ERMINATION
V
CC
- 2V
50
Ω
50
Ω
RTT
Z
o
= 50
Ω
Z
o
= 50
Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
drive 50
Ω
transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
T
ERMINATION
FOR
LVPECL O
UTPUTS
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o
= 50
Ω
Z
o
= 50
Ω
FOUT
FIN
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