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參數(shù)資料
| 型號： | ICS84314-02 |
| 英文描述： | 700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER |
| 中文描述： | 700MHz的，CRYSTAL-TO-3.3V/2.5V LVPECL的頻率合成瓦/扇出緩沖器 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 196K |
| 代理商： | ICS84314-02 |
84314AY-02
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 17, 2005
2
Integrated
Circuit
Systems, Inc.
ICS84314-02
700MH
Z
, C
RYSTAL
-
TO
-3.3V/2.5V LVPECL
F
REQUENCY
S
YNTHESIZER
W
/F
ANOUT
B
UFFER
PRELIMINARY
nP_LOAD input is initially LOW. The data on inputs M0 through
M8 is passed directly to the M divider. On the LOW-to-HIGH tran-
sition of the nP_LOAD input, the data is latched and the M divider
remains loaded until the next LOW transition on nP_LOAD or until
a serial event occurs. As a result, the M bits can be hardwired to
set the M divider to a specific default state that will automatically
occur during power-up. In parallel mode, the N output divider is
set to 2. In serial mode, the N output divider can be set for either
÷
1,
÷
2,
÷
4 or
÷
8. The relationship between the VCO frequency,
the crystal frequency and the M divider is defined as follows:
fVCO =16
The M value and the required values of M0 through M8 are shown
in Table 3B, Programmable VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock for a 16MHz refer-
ence are defined as 125
≤
M
≤
350. The frequency out
is defined as follows:
fout = fVCO
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA bits
with the rising edge of S_CLOCK. The contents of the shift regis-
ter are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N out-
put divide values are latched on the HIGH-to-LOW transition of
S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is
passed directly to the M divider and N output divider on each
rising edge of S_CLOCK.
S
ERIAL
L
OADING
NOTE: The functional description that follows describes
operation using a 16MHz crystal. Valid PLL loop divider
values for different crystal or input frequencies are defined
in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS84314-02 features a fully integrated PLL and there-
fore requires no external components for setting the loop
bandwidth. A parallel-resonant, fundamental crystal is used
as the input to the on-chip oscillator. The output of the os-
cillator is divided by 16 prior to the phase detector. With a
16MHz crystal, this provides a 1MHz reference frequency.
The VCO of the PLL operates over a range of 250MHz to
700MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by ad-
justing the VCO control voltage. Note that for some values
of M (either too high or too low), the PLL will not achieve
lock. The output of the VCO is scaled by a divider prior to
being sent to each of the LVPECL output buffers. The divider
provides a 50% output duty cycle.
The programmable features of the ICS84314-02 support
two input modes to program the M divider. The two input
operational modes are parallel and serial.
Figure 1
shows
the timing diagram for each mode. In parallel mode, the
F
UNCTIONAL
D
ESCRIPTION
F
IGURE
1. P
ARALLEL
& S
ERIAL
L
OAD
O
PERATIONS
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8
nP_LOAD
S_LOAD
Time
P
ARALLEL
L
OADING
t
S
t
H
t
S
t
H
t
S
M, N
*
NULL
*
NULL
SSC0
**
N1
**N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
*NOTE:
The NULL timing slot must be observed.
**NOTE:
“N” can only be controlled through serial loading.
=
16
2M
fxtal x
N
1
x
N
1
x
e
u
V
c
o
L
1
N
e
u
V
c
o
L
0
N
e
d
D
t
u
÷
1
p
t
u
O
N
0
0
1
1
0
1
0
1
÷
)
a
D
p
u
w
o
P
(
2
÷
4
÷
8
T
ABLE
1A. N O
UTPUT
D
IVIDER
F
UNCTION
T
ABLE
(S
ERIAL
L
OAD
)
0
C
0
1
S
S
e
S
p
D
B
C
u
w
o
P
S
S
)
a
D
(
f
O
T
T
ABLE
1B. SSC F
UNCTION
T
ABLE
相關PDF資料 |
PDF描述 |
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| ICS84314A02L | 700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER |
| ICS84314AY02 | 700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER |
| ICS84314AY-02 | 700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER |
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| ICS84314AY-02LFT | 700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS84314A02L | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER |
| ICS84314AY | 制造商:ICS 制造商全稱:ICS 功能描述:350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER |
| ICS84314AY02 | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER |
| ICS84314AY-02 | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER |
| ICS84314AY-02LF | 功能描述:IC SYNTHESIZER 700MHZ 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™ 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
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