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參數(shù)資料
| 型號(hào)： | ICS843101IAG-100T |
| 英文描述： | FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 100MHZ FREQUENCY MARGINING SYNTHESIZER |
| 中文描述： | FEMTOCLOCKS⑩晶體到的LVPECL 100MHZ輸出頻率裕合成器 |
| 文件頁數(shù)： | 11/17頁 |
| 文件大小： | 243K |
| 代理商： | ICS843101IAG-100T |
843101AGI-100
www.icst.com/products/hiperclocks.html
REV. A OCTOBER 20, 2005
11
Integrated
Circuit
Systems, Inc.
ICS843101I-100
F
EMTO
C
LOCKS
C
RYSTAL
-
TO
-LVPECL
100MH
Z
F
REQUENCY
M
ARGINING
S
YNTHESIZER
PRELIMINARY
T
ERMINATION
FOR
3.3V LVPECL O
UTPUT
The clock layout topology shown below is a typical ter-
mination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
V
CC
- 2V
50
Ω
50
Ω
RTT
Z
o
= 50
Ω
Z
o
= 50
Ω
FOUT
FIN
RTT =
Z
o
1
((V
OH
+ V
OL
) / (V
CC
– 2)) – 2
3.3V
125
Ω
125
Ω
84
Ω
84
Ω
Z
o
= 50
Ω
Z
o
= 50
Ω
FOUT
FIN
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
F
IGURE
4B. LVPECL O
UTPUT
T
ERMINATION
F
IGURE
4A. LVPECL O
UTPUT
T
ERMINATION
outputs are designed to drive 50
Ω
transmission lines.
Matched impedance techniques should be used to maxi-
mize operating frequency and minimize signal distor-
tion.
Figures 4A and 4B
show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compat-
ibility across all printed circuit and clock component pro-
cess variations.
I
NPUTS
:
C
RYSTAL
I
NPUT
:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating. Though
not required, but for additional protection, a 1k
Ω
resistor can be
tied from XTAL_IN to ground.
CLK I
NPUT
:
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1k
Ω
resistor can be tied from the CLK input to ground.
LVCMOS C
ONTROL
P
INS
:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
Ω
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVPECL O
UTPUT
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ICS843-106 | 制造商:ICS 制造商全稱:ICS 功能描述:106.25MHZ, LVCMOS, LVPECL DUAL OUTPUT OSCILLATOR |
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| ICS8431-21 | 制造商:ICS 制造商全稱:ICS 功能描述:350MHZ, LOW JITTER, CRYSTAL OSCILLATOR-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| ICS84314 | 制造商:ICS 制造商全稱:ICS 功能描述:350MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER |
| ICS84314-02 | 制造商:ICS 制造商全稱:ICS 功能描述:700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER |
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